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Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

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Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#101
post #69
post #59

Earlier quoted context omitted.

It doesn't seem so. I think they're just switching the internal processors that do LBA translation, error correction, bad-block marking etc over to RISC. And then their marketing department took that decision and ran with it in a completely different direction. The key line is "... transitioning its own consumption of processors – over one billion cores per year – to RISC-V."

Far more likely is that the SSD controllers that WD-SanDisk will create (that are the value-add difference between commodity NAND and good SSDs) will now use RISC-V cores. Samsung has a 5-core controller in its drives; I would guess that licensing costs are a pretty hefty chunk of the BOM for creating the controller

>> Samsung has a 5-core controller in its drives

Samsung is developing their own RISC-V cores too...

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#102
post #92

Earlier quoted context omitted.

WD made it clear in there talk that this wasn't about saving on costs, but rather having control over the innovation in the data space. I don't see any reason to doubt them. It's an incredible risk to switch their entire company over to a still-growing ISA. But being able to design and modify any particular core as they see fit without having to talk to lawyers or negotiate a new contract... that's an incredible powe…

RISC-V is certainly more unencumbered, but there's always the ARM architecture license too. Pricey, but you can modify and build on a relatively more mature ISA

An architectural license doesn't give you free reign to extend the ISA, just to create your own implementation of the standard ISA.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#103

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

That, and I'm kind of disappointed everyone has drunk the RISC kool-aid.

Agree completely. One only has to look at the prominence (or lack thereof) of MIPS, the other "pure RISC" architecture, to see that it's not known for being anything other than cheap. Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS; and their performance (or once again, lack thereof) is notable. ARMs are, internally, much closer to x86 than MIPS or RISC-V.

That said, there's always a place for cheaper and simpler 32-bit cores in applications like HDD controllers, where high performance and efficiency is not a primary goal.

If you had a language/compiler that took better advantage of a stack architecture, or even a CISC architecture, the performance would probably be just as good if not better.

Stack architectures are pretty easy to generate code for and have a (slight) advantage with code density, but their memory access patterns are hard to optimise for, and they are even harder to make superscalar.

On the other hand, I think a "CISC-V" could become an interesting and possibly quite competitive alternative to x86.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#104
post #28

From the headline, I would guess WD is putting a user accessible CPU in each of their disk drives, idea being that if you have a CPU living close to the drive, then e.g. map+reduce workloads can be more efficiently executed. Instead of going with ARM or Intel, I guess the CPU's are using some less famous architecture called RISC-V. Then I read the article, and the article is so full of buzzwords and genericisms that…

That would mean that the bandwidth from the hard drive is a large bottleneck, which I have a hard time believing is true.

AFAIK Doing error correction on 4K blocks of data is fairly non-trivial. Using custom instructions may be a benefit here too.

https://www.seagate.com/tech-insights/advanced-format-4k-sec...

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#105
post #55

If you're interested in what's going on at the RISC-V Workshop, you might want to follow my live blog here: http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-...

Let me thank you for providing the excellent write-up. I eagerly wait for news from lowRISC in hope for a SBC with general purpose Linux support. This would open up the hardware in general, and thus be a major step in a good direction.

I do have a question, though. Is there any plan for working on an architecture for massively parallelizable workloads, like graphics, artifical neural networks and simulations? Especially the talk by Dave Ditzel seems relevant to this. Even without competitive performance, that would be another major step. It would not only improve the situation by the amount of the necessary efforts for that, but by raising the bar for all the other vendors by being compared to that.

There is a factor between your work and the impact on the ecosystem, and I guess it is significantly higher than one.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#106
post #53

I remember RISC's back in the late 80's/early 90's. CISC's bullied them away and we've been stuck in Intel's quagmire every since. Anytime there's an attack on the status quo, the established players feign concern and beat back the attack then return to the way things were (remember Negroponte's $100 laptop and the netbook response?) No idea how this will pan out.

x86s were about the most riscy of the cisc processors - 99.9% of instructions that access memory perform an access to a single address, no double indirect accesses no move memory to memory accesses, not 21 TLB misses on a single instruction (meaning a program might have to have enough memory to get all 21 page table pages and the underlying data pages (42 pages) to make progress) - that sort of thing.

The CISC->RISC thing largely happened because the ratio of cpu speeds and memory speeds changed, low end CPUs got caches, they moved on chip, instruction decoding started to be an issue, the x86s were riscy enough that they survived that change

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#107

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Agree completely. One only has to look at the prominence (or lack thereof) of MIPS, the other "pure RISC" architecture, to see that it's not known for being anything other than cheap. Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS; and their performance (or once again, lack thereof) is notable. A…

I'd figure at least from the perspective of the JVM and the CLR, you'd have less of an impedance mismatch on a stack machine. And with most compiled languages being conceptually very stack-y, I doubt it would hurt there either.

That, and you could save on instruction bandwidth since the operands could be implicit stack offsets instead of having to be specified in the instruction. (I believe Moore's GreenArray chips packed four instructions to the word.)

It might be a dead-end, or there could be some serious potential that is just being overlooked. Everyone is so accustomed to register machines (CISC or RISC) these days that it may be a while before the idea is reevaluated.

edit: Sorry! Just read this back, and realized I just repeated what you wrote in different words.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#108
post #53

I remember RISC's back in the late 80's/early 90's. CISC's bullied them away and we've been stuck in Intel's quagmire every since. Anytime there's an attack on the status quo, the established players feign concern and beat back the attack then return to the way things were (remember Negroponte's $100 laptop and the netbook response?) No idea how this will pan out.

It wasn't that CISC won or that RISC lost, it was that the architectures got so blurry you couldn't tell one from the other. There's so much microcode in a CPU now that the instruction set is just the icing layer on the cake. Internally there's surprising amounts of commonality between PowerPC, ARM and x86 type chips. Plus PowerPC started to adopt CISC-like instructions, x86-64 started to adopt RISC-like features suc…

Actually most real RISC CPUs have no microcode, and if they do it's really just the same instruction set running out of an exception handler, not hardwired stuff on some other lower level private ISA

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#109
Well what I find interesting here is if they are able to manufacture chips with 7nm litography. Aren't intel and samsung who I belive to be the leaders in the field, still at 14 nm? In case WD manages to beat them to the market with this technology at least there will be a lot of hype around this.

As far as binary compability is concerned this is more or less a thing of the past. The way I see it js and other interpreted languages provide for the most vibrant ecosystem at the moment. Where we have package management running not over only kernels but also distributions.

Before this developers have gotten really acustomed to compiling into platform independent bytecode. And even windows which in comparison with Linux has been ported to few platforms is by no means impossible to move over to a new instruction set. As have been demonstrated multiple times. Even C itself was developed to make few assumptions in regards to the metal. If you please, excuse me for reiterating facts well known to the average HN reader.

Furthermore with developers more or less requiring to work with open source software as it makes debugging and making use of other developers experiences easier. The probability that you will be stuck with CPU specific binaries of any given program is slim.

Now the problem is "only" to find programmers capable of programming 4096 CPU cores to operate well simultaneously, in a world where it's completely accepted and right, for a text editor to eat up hundreds of megabytes of ram displaying the source code for a hello world program. Also for this to truly make a dent the development has to span all the way from the metal via the kernel and to the actual application.

Unfortunately I am afraid that the open license will mean very little, from a freedom point of view as they take this route out of the pragmatic reasons, briefly mentioned above, not to make an ideological stand. Nonetheless it's a step forward so I'll try to supress my cynicism.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#110
post #70

Earlier quoted context omitted.

In order to move the reader head inside your drive and to communicate with the host CPU you need microprocessors in your hard driver, really tiny ones. Now, instead of paying ARM for licences to use them WD is using open source processors that don't come with fees besides what it takes to manufacture them.

This is the right answer...they already use ARM, they want a one-time-fee license instead of royalties. Trying to shave a little margin.

Is this confirmed though?

Were they using ARM? ( Proberly, but may not be in everything they use ) Are they switching over from ARM? Or simply moving their inhouse controller to RISC-V?

The one time license fee were suppose to be a lot cheaper if you are shipping in billions of unit.

Because if they are switching from ARM, I think of it as ARM being lazy and not winning the battle they ought to win, purely from a business perspective.

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