Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
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Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#2Would anyone familiar with the various qualities of FPGA boards care to weigh in on how to pick a good development board for this project? I personally know nothing about FPGA specs.
Additionally, the first blog post in this series can be found at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#3Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#4Would anyone familiar with the various qualities of FPGA boards care to weigh in on how to pick a good development board for this project? I personally know nothing about FPGA specs. Additionally, the first blog post in this series can be found at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...
The Terasic DE0-nano (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=E...) is a great board for soft CPU's. It's cheap, has a decent size FPGA and external SDRAM. The Altera tools are free and run under Windows/OSX/Linux.
I've used this board for my own soft CPU (http://jamieiles.github.io/oldland-cpu/) and it's a rewarding project!
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#5Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.
Hey - author here. I'm not wanting to learn industry practices, it's a hobby project. May look into things like that later, though. The other article parts have the disclaimer that says I have no idea what I'm doing ;) Cheers for the feedback :)
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#6Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.
Not a great codebase. That's putting it lightly.
It does have a pipeline BTW.
Industry is so different I don't know where to start complaining.
Xilinx tools are not used for simulation usually because they suck and we generally pay those other tool vendors for their stuff so we might as well use them.
Given that newbies don't want to pay, maybe Xilinx is the best. I don't know much about the free stuff.
Looking at previous posts, there is so much behavioral code everywhere. We don't write a lot behavioral stuff in VHDL usually. There are higher level languages for behavioral code. Once again, you probably have to pay for those tools so maybe you have no good choices other that behavioral VHDL.
IF generic you are stuck with the Xilinx behavioral VHDL, I still would NOT write the behavioral stuff to be a cycle accurate representation of the design. You are just as likely to make a mistake in the behavioral as the RTL. Then when you test the behavioral model against the RTL you will spend half your time debugging the behavioral side. Thinking ahead really helps.
The whole approach is wonky from the start. If it were me I would think about the project as a whole and plan ahead. The design is complex in terms of verification. We always assume that every design is complex to verify! If not you wouldn't need HW in the first place.
There will be lots of tests. How does the test bench run a big suite of tests and report failures? You do not want to look at waveforms unless your test finds a failure. This blog jumps straight to waves!
I would start from the whole design first. Figure out the interfaces. Then try to express those interfaces in terms of transactions.
In fact, maybe don't even start writing VHDL as an expression of the design. Most times in industry we design via documents first. Docs express how the HW will work at a high level and how it will be verified. It breaks the design down into modules. It explains the interfaces between modules. These interfaces become possible points for the verification to look at. The test bench compares the simulated result with a golden reference when it sees a transaction event at the interface and reports a mismatch.
The point is create project infrastructure first via planning. Have a big picture view of how it's all going to be thoroughly tested automatically each time new code is committed. In industry on top of directed tests, we use constrained randomized tests. We have to determine whether we have covered everything. So we need functional coverage. All this is designed first BEFORE we play around with flops.
We can tolerate a lot of craptastic VHDL/Verilog code in industry because at the higher levels it looks neat and tidy and it is all tested vigorously.
Basically don't follow any stuff from academia because I would bet those guys have never delivered a commercial product. Educational material from tools guys is almost as bad for similar reasons. No one can hold your hand so you have to use your brain.
I probably vented too much here. It's just tough to see engineering done badly.
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#7Would anyone familiar with the various qualities of FPGA boards care to weigh in on how to pick a good development board for this project? I personally know nothing about FPGA specs. Additionally, the first blog post in this series can be found at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...
The Terasic DE0-nano ( http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=E... ) is a great board for soft CPU's. It's cheap, has a decent size FPGA and external SDRAM. The Altera tools are free and run under Windows/OSX/Linux. I've used this board for my own soft CPU ( http://jamieiles.github.io/oldland-cpu/ ) and it's a rewarding project!
Happy to provide some quick feedback on your coding style:
Please don't use initial blocks to initialize values, use an always block with reset. That will also solve the issue of having multiple drivers per signal (bad). Also, don't load memories from the RTL, do that from the test bench (using hierarchical references).
initial begin
$readmemh({`OLDLAND_ROM_PATH, "decode.hex"}, microcode, 0, 127);
rd_sel = 4'b0;
update_rd = 1'b0;
alu_opc = 5'b0;
branch_condition = 4'b0;
alu_op1_ra = 1'b0;
alu_op1_rb = 1'b0;
alu_op2_rb = 1'b0;
mem_load = 1'b0;
mem_store = 1'b0;
mem_width = 2'b0;
pc_plus_4_out = 32'b0;
instr_class = 2'b0;
is_call = 1'b0;
update_flags = 1'b0;
update_carry = 1'b0;
cr_sel = 3'b0;
write_cr = 1'b0;
spsr = 1'b0;
is_swi = 1'b0;
is_rfe = 1'b0;
i_valid = 1'b0;
cache_instr = 1'b0;
exception_start_out = 1'b0;If someone knows of a community like HN that can write great Verilog, let me know.
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#8[deleted]
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#9Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.
Hey - author here. I'm not wanting to learn industry practices, it's a hobby project. May look into things like that later, though. The other article parts have the disclaimer that says I have no idea what I'm doing ;) Cheers for the feedback :)
Uh oh. I didn't realize you were actually on HN. Apologies if my other spiel seems too harsh.
Perhaps the better sounding term would be "engineering practices" rather than "industry practices". If it's a hobby, you still want to get a good result out of your effort. That principle in industry still applies to the hobbyist IMO.
The signal names issue that alain94040 mentioned was just an example of one problem with the code.
Assuming the desired result is to get running on an fpga, I think you need to take a step back for a second and look at the target environment you want to run on and plan out how it will all work.
Re: Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching
#10Not a great codebase, if you are trying to learn the industry's best practices. For instance, I recommend naming your RTL signals based on which pipeline stage they belong to. Assuming this thing even has a pipeline.
So, where is a great codebase for somebody who wants to learn?