Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake' • Hacker News Board

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#41

Post by MikeNomad » Mon, Jul 06, 2015, 6:26 PM UTC

MikeNomad wrote: post #24

I would think the Cannonlake delay is more about HVAC / Clean Room environmental controls for particles at 10nm than the actual chip fab.

Yeah, the litho process is largely the same. Thanks for furthing the idea I was trying to get across: The hang up is not in the production process, it's in the environmental controls.

To put it another way, if I manufacture on a smaller die size, I have to control for smaller pieces of junk in the air. If I don't, I will get poor (read, not cost effective) yields, making production in that environment a bad business decision.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#42

Post by psk » Mon, Jul 06, 2015, 6:30 PM UTC

solomatov wrote: post #17

bryanlarsen wrote: post #12

Earlier quoted context omitted.

Reference "The Boy who cried Wolf". That pronouncement has been made and proven wrong way too many times for anybody to take it seriously. Eventually the wolf will come and the limit will be reached, but until it happens nobody will believe it.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

I'm curious, what are the quantum effects at that size?

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#43

Post by solomatov » Mon, Jul 06, 2015, 6:48 PM UTC

psk wrote: post #42

solomatov wrote: post #17

Earlier quoted context omitted.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

I'm curious, what are the quantum effects at that size?

See, for example, https://en.wikipedia.org/wiki/Quantum_tunnelling

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#44

Post by ZenoArrow » Mon, Jul 06, 2015, 7:53 PM UTC

marcosdumay wrote: post #37

ZenoArrow wrote: post #26

Earlier quoted context omitted.

It'll be interesting to see the parts that silicon photonics and molecular assembly come to play in meeting the future process nodes. I agree with those who say we'll reach a cost barrier before we reach a technical barrier. If I were to make a wild guess, I'd say 7nm will be that limit, and that it'll be about 5 years away (Moore's Law is already broken and isn't likely to be fixed any time soon, hence the slower ti…

A cost barrier is the most common manifestation of a technical barrier. There's no way silicon microlitography will keep working once transistors are just a few atoms big. In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore.

>"There's no way silicon microlitography will keep working once transistors are just a few atoms big."

That's why I mentioned molecular assembly.

>"In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore."

That's why I mentioned silicon photonics.

> "A cost barrier is the most common manifestation of a technical barrier."

It can be, but not always. We can definitely move beyond 7nm, we've already done it in the lab, but knowing if we can find ways to afford the costs of manufacturing below that point is not as clear.

http://www.purdue.edu/newsroom/research/2012/120219KlimeckAt...