Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing • Hacker News Board

Re: Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing

#11

Post by jeffbush » Wed, Jun 24, 2015, 6:20 PM UTC

krupan wrote: post #10

jeffbush wrote: post #6

Earlier quoted context omitted.

I use Verilog, so I'm not as familiar with the state of VHDL tools. I've found Verilator to be much faster (although it cuts some corners) than the free versions of Modelsim. It's fairly stable and supports most of the core synthesizable SystemVerilog constructs.

Verilator only supports a synthesizable subset of verilog, so if you want to write a testbench you are either going to be writing it with synthesizable verilog ( not recommended) or with C++ (or something else you figure out how to link in).

The main thing it is missing is delays (it does have non-synthesizable constructs like $display). However, if you're developing a processor, most of your testing is executing programs. For that, you don't need a complex testbench: just load the executable code into your memory and toggle the clock.

Re: Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing

#12

Post by houli » Wed, Jun 24, 2015, 7:02 PM UTC

therobot24 wrote: post #2

I remember doing this stuff in my computer architecture classes, Xilinx is incredibly powerful but also incredibly painful to use.

Yep my computer architecture class used the same tools. It's only been 2-3 months since but I'm already having painful memories of the syntax errors and nights of staring at red "UUUUUUUU" undefined registers.

Re: Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, Register File, Testing

#13

Post by baldjinx » Wed, Jun 24, 2015, 8:10 PM UTC

therobot24 wrote: post #2

I remember doing this stuff in my computer architecture classes, Xilinx is incredibly powerful but also incredibly painful to use.

I agree that the Xilinx tools are not so easy to use, but I feel that they are far from painful.

I am amazed with the functionality of the free version of ISE (both in simulation and floor plan design). I have used this software to prototype and implement a 3rd order pipelined sigma-delta modulator on a FPGA, and several simple CPLD projects which didn't require simulation.

The simulator is far from crippled. I was able to read input from a binary test vector file into the simulator, run it though the model, and save the output to file. I found this very useful during development to compare the VHDL implementation with the prototype I had written in C.