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Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

labs.domipheus.com

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Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#41

Post by mng2 »

rdc12 wrote: post #36
andmarios wrote: post #31

We did similar projects as part of our ECE degree. In general we would start with boolean algebra and logic design, then proceed to computer organization and last to computer architecture (one semester each). Your project would be at the computer organization level. IIRC adding a pipeline would move it to computer architecture level. I understand that reading outside a class may be a bit boring, but these courses gav…

What is the difference between Computer Organization and Computer Architecture?

COD is intended for undergrad courses, CA is more graduate level.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#42

Post by lfowles »

rdc12 wrote: post #38
lfowles wrote: post #37

Earlier quoted context omitted.

As of 2007-2011, Patterson and Hennessy books were in use in courses I took as well. Great stuff, but the treatment on GPUs was a little out of date even a year or two after being published (GPGPU was just getting started and evolving rapidly).

Their Computer Organization and Design, had a new edition in 2013, that may cover GPU stuff better, havn't read it myself thou. Still havn't seen a book that covers SIMD very well?

* Features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples throughout the book

Sounds promising. The 4th edition just had the GPU content stuffed into an appendix.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#43

Post by alain94040 »

domipheus wrote: post #25
alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

Cheers for the tips. I'll eventually move to Verilog, but as others point out, I think it's good to walk before I run. Regarding pipelining, I'm getting right on it - and the iterative benchmarking is something I plan to do. Thanks again :)

Also, feel free to contribute to the Verilog tutorial I started for software engineers, it's on WikiBooks at https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...

VHDL is dead in the industry(). While VHDL is slightly better for teaching, why not learn directly what everyone else uses? Also, because VHDL is such a pain to support for CAD tools, more tools support Verilog only, or support VHDL as a second-class citizen.

() my european friends hate me each time I say that, but it's true.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#44

Post by hharnisch »

> Verilog is the C99 of the HDL world, and you can get in quite a mess as a beginner if you don’t understand it well enough.

I found both to have their little quirks, but personally liked Verilog syntax a little better - modules concept made a lot more sense coming from a software background. Do you have an existing instruction set you're planning on supporting?

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#45

Post by hobolord »

alain94040 wrote: post #43
domipheus wrote: post #25

Earlier quoted context omitted.

Cheers for the tips. I'll eventually move to Verilog, but as others point out, I think it's good to walk before I run. Regarding pipelining, I'm getting right on it - and the iterative benchmarking is something I plan to do. Thanks again :)

Also, feel free to contribute to the Verilog tutorial I started for software engineers, it's on WikiBooks at https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for... VHDL is dead in the industry( ). While VHDL is slightly better for teaching, why not learn directly what everyone else uses? Also, because VHDL is such a pain to support for CAD tools, more tools support Verilog only, or support VHDL as a second-c…

Yeah I was taught in VHDL but my prof acknowledged that it's mainly because it's better as an educational tool. He argued that it's easier to go from VHDL to Verilog after learning the strict practices, and that it leads to just better programming practices in the industry
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