A big reason why the fpga companies keep everything secret is to protect themselves against patent lawsuits (exactly as gpu companies). So once again we can see how the patent system is good for innovation....
The Lack of Open Tooling for FPGAs
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Re: The Lack of Open Tooling for FPGAs
#12I'll offer a guess as to why the FPGA manufacturers are hostile to open tools. Open tools reveal the internal details of their FPGA hardware which is their bread and butter. I think it is probably the wrong approach, but that sort of thinking is common around intellectual "property."
I am OP
You are correct some of the information required to build a computer for these chips are 'internal' details. However they already have strict patents on most of it, and knowing the configuration bits of a chip and the the delay of various paths is not going to give away their fabrication technique. They could potentially release just enough details to satisfy compiler writers instead of making us do it ourselves so we try to rip every details out of it.
Re: The Lack of Open Tooling for FPGAs
#13A big reason why the fpga companies keep everything secret is to protect themselves against patent lawsuits (exactly as gpu companies). So once again we can see how the patent system is good for innovation....
I am OP
Hmm, that is actually a good point. Might as well not draw any attention to yourself incase some ass hole has a patent on the concept of moving electrons down copper or something insane.
Re: The Lack of Open Tooling for FPGAs
#14Open FPGAs would be disruptive to the status quo, that's why they are closed. Right now many technologies like video cards are wandering in the desert, adding on more and more opaque layers rather than providing general purpose computing. So that's set simulation back at least a decade or two and hindered progress in fields like AI.
I just want to address one of the main complaints about FPGAs - that they require more chip area to route logic. This is not as big of a deal as it sounds because today 3/4 of a chip's area or more is often dedicated to mundane things like cache.
Also since there has been little progress in breaking the 3 GHz barrier since the early 2000s, everything is moving towards higher transistor counts. So the added cost of layout goes down over time and after about 3 years is on par with the previous generation. So we have a chicken and egg problem where true general purpose parallel computing can't get off the ground because it's perceived as too expensive, but it's too expensive because it hasn't gotten off the ground yet.
Breaking that chicken and egg cycle by opening FPGAs could trigger an overnight adoption of them, even greater than when Bitcoin triggered renewed interest in ASICs.
Re: The Lack of Open Tooling for FPGAs
#15Would somebody knowledgeable care to comment on how tools like Bluespec SystemVerilog play into this discussion if at all? Disclaimer: I know little enough about EE that this question might be nonsensical.
Re: The Lack of Open Tooling for FPGAs
#16The tools for FPGAs are horribly clunky and extremely difficult to script since most are Windows GUI based. Glad to see people working to rectify this.
Some of the Xilinx and Altera tools come with and install Cygwin (and tcl). Watching WINE install Cygwin is good for a chuckle.
Re: The Lack of Open Tooling for FPGAs
#17Would somebody knowledgeable care to comment on how tools like Bluespec SystemVerilog play into this discussion if at all? Disclaimer: I know little enough about EE that this question might be nonsensical.
SystemVerilog is a Hardware Description Language (HDL), which is what the first step in the process. The HDL synthesis is the level just above the part of the process where the major tooling issues referenced exist, since synthesis generally isn't specific to a particular chip vendor and, as noted, is also a necessary step before laying out an ASIC.
Re: The Lack of Open Tooling for FPGAs
#18I'll offer a guess as to why the FPGA manufacturers are hostile to open tools. Open tools reveal the internal details of their FPGA hardware which is their bread and butter. I think it is probably the wrong approach, but that sort of thinking is common around intellectual "property."
I am OP You are correct some of the information required to build a computer for these chips are 'internal' details. However they already have strict patents on most of it, and knowing the configuration bits of a chip and the the delay of various paths is not going to give away their fabrication technique. They could potentially release just enough details to satisfy compiler writers instead of making us do it oursel…
Often times there are clever optimizations and work around that have to be implemented to work around internal limitations that they don't publish so as not to give their competitor marketing advantages.
What we should be pushing for are cross platform tool. Being open-source isn't something that I necessarily would care about as an EE in this particular case. It doesn't get me anything I don't with vendor tools. The BIGGEST thing in FPGA/ASIC design is certainty. Error in the tool costs me time and money.
You'll find it difficult to convince anyone to a tool that isn't supported by the vendor because errors and bugs, in the tool or the tool data, won't get resolved quickly.
Most of the money in ASIC/FPGA is spent on "verification" either as pre-build/pre-tested cores or as tools that do verification, such as formal logic tools.
Re: The Lack of Open Tooling for FPGAs
#19The tools for FPGAs are horribly clunky and extremely difficult to script since most are Windows GUI based. Glad to see people working to rectify this.
Not just FPGA tools, pretty much the whole EE industry. Few days ago I had trouble saving results from a semiconductor analyzer. The problem? Path had spaces in it. If you have the time to display a warning that it doesn't support spaces (on windows!), you should be able to fix the issue. Just imagine how bloated their codebase that you can't fix issues like this easily. Recently I was trying to use ModelSim (HDL sim…
Tcl script errors on Altera tools - brings back lots of bad memories... It seems like as soon as you try to break out of the standard way of doing things the scripts break.
Re: The Lack of Open Tooling for FPGAs
#20The tools for FPGAs are horribly clunky and extremely difficult to script since most are Windows GUI based. Glad to see people working to rectify this.
Not just FPGA tools, pretty much the whole EE industry. Few days ago I had trouble saving results from a semiconductor analyzer. The problem? Path had spaces in it. If you have the time to display a warning that it doesn't support spaces (on windows!), you should be able to fix the issue. Just imagine how bloated their codebase that you can't fix issues like this easily. Recently I was trying to use ModelSim (HDL sim…
These codebases are often sub-contracted to the lowest bidder. Which explains all of the issues that everybody has on a daily basis. Sadly, hardware is a race to the bottom, and there is little motivation to provide quality tools.