How FPGAs work, and why you'll buy one (2013)
1–10 of 110 posts
Re: How FPGAs work, and why you'll buy one (2013)
#2Did the followup article ever get written? I didn't find anything with a search for the proposed title on either his site or Google.
Re: How FPGAs work, and why you'll buy one (2013)
#3Re: How FPGAs work, and why you'll buy one (2013)
#4Re: How FPGAs work, and why you'll buy one (2013)
#5Is there a possibility to use just-in-time compilers to port software to FPGAs? I can see how that could be used to accelerate applications written on bytecode languages (i.e. mostly everything in your mobile phone) to near-assembly speeds.
As for JIT-ing, compilation times for FPGAs are often in the hours, and the software involved is unfortunately proprietary (and not easily integrated with). There are some field-reconfiguration libraries, but I am not sure to what extent real-world applications compile new Verilog on the fly..
Re: How FPGAs work, and why you'll buy one (2013)
#6A sequel is in the making, titled "Why you won't buy an FPGA" Did the followup article ever get written? I didn't find anything with a search for the proposed title on either his site or Google.
Re: How FPGAs work, and why you'll buy one (2013)
#7Writing code that is concurrent by default is a massive paradigm shift when all I had been exposed to at that point were procedural languages.
Re: How FPGAs work, and why you'll buy one (2013)
#8So the overhead for programmability is higher than a DSP/GPU if you want to gain over and above them.
I do wonder if there's a sweet spot in here somewhere that's basically a sea of DSP or GPU (maybe better to call them stream processing units) with programmable wiring and some specialised ALUs/FP units mixed in that can also use the wiring allowing you to create special one-cycle fixed function ops?
Re: How FPGAs work, and why you'll buy one (2013)
#9The trouble I had with FPGAs is how radically different languages like Verilog and VHDL are when compared to languages like Java, Python, or C++. Writing code that is concurrent by default is a massive paradigm shift when all I had been exposed to at that point were procedural languages.
Say
e.g:
state read_input =>
reg_a
state multiply_input_by_10 => reg_b
state send_to_output => finish_reg
and then parallel to that you would have finish_wire
or something like that, sorry for the bad example but definitely use state machinesRe: How FPGAs work, and why you'll buy one (2013)
#10The trouble I had with FPGAs is how radically different languages like Verilog and VHDL are when compared to languages like Java, Python, or C++. Writing code that is concurrent by default is a massive paradigm shift when all I had been exposed to at that point were procedural languages.