The J1 Forth CPU • Hacker News Board

Re: The J1 Forth CPU

#21

Post by _yosefk » Wed, Apr 15, 2015, 5:45 AM UTC

e12e wrote: post #18

_yosefk wrote: post #15

Earlier quoted context omitted.

"A fully fledged independent computer"? You need several such "computers" to compute an MD5 checksum according to an application note at their site. Anything anyone in the industry dares to call a "core" (apart from NVIDIA's ALUs misnamed as "CUDA cores" or whatever) blows a GA "computer" out of the water, in particular, in terms of memory (you'll get kilobytes or more likely tens of kilobytes of cache and/or RAM per…

It's an interesting chip. You can implement a SRAM interface[1] using a few cores. And also generate a VGA signal[2]. Or run 10base 10 ethernet[e]. It's probably better to compare it with a FPGA that allows for rapid programming, than a multicore computer. Only you can sort of configure the whole thing as a SOC. Which has great power management. I'd love to see some updates from Greenarrays -- there hasn't been much…

How about a DRAM interface? That is both necessary for sufficiently complex applications, and damned hard. An FPGA can do it, for some frequency (though many FPGAs come with a hard DRAM interface to save area and improve the frequency.) This thing? I rather doubt.

Also, "implement an SRAM interface" - perhaps, but not one particularly easy to program against, I believe.

Re: The J1 Forth CPU

#22

Post by e12e » Wed, Apr 15, 2015, 8:47 AM UTC

_yosefk wrote: post #21

e12e wrote: post #18

Earlier quoted context omitted.

It's an interesting chip. You can implement a SRAM interface[1] using a few cores. And also generate a VGA signal[2]. Or run 10base 10 ethernet[e]. It's probably better to compare it with a FPGA that allows for rapid programming, than a multicore computer. Only you can sort of configure the whole thing as a SOC. Which has great power management. I'd love to see some updates from Greenarrays -- there hasn't been much…

How about a DRAM interface? That is both necessary for sufficiently complex applications, and damned hard. An FPGA can do it, for some frequency (though many FPGAs come with a hard DRAM interface to save area and improve the frequency.) This thing? I rather doubt. Also, "implement an SRAM interface" - perhaps, but not one particularly easy to program against, I believe.

I don't think it's a particularly good fit if what one really wants is the equivalent of a "PC" (ie: n cores of ~broadwell cpu with x gigs of ram) -- I tried to highlight that it is an entirely different system, and one which allows for some interesting streaming, straight forward, approaches to solving many problems. You won't be running python on this thing, but that doesn't mean that you can't do some interesting signal processing -- at extremely low power.

Maybe "really, really smart dsp" is a way to look at it...

Re: The J1 Forth CPU

#23

Post by _yosefk » Wed, Apr 15, 2015, 11:35 AM UTC

e12e wrote: post #22

_yosefk wrote: post #21

Earlier quoted context omitted.

How about a DRAM interface? That is both necessary for sufficiently complex applications, and damned hard. An FPGA can do it, for some frequency (though many FPGAs come with a hard DRAM interface to save area and improve the frequency.) This thing? I rather doubt. Also, "implement an SRAM interface" - perhaps, but not one particularly easy to program against, I believe.

I don't think it's a particularly good fit if what one really wants is the equivalent of a "PC" (ie: n cores of ~broadwell cpu with x gigs of ram) -- I tried to highlight that it is an entirely different system, and one which allows for some interesting streaming, straight forward, approaches to solving many problems. You won't be running python on this thing, but that doesn't mean that you can't do some interesting…

Interesting signal processing - perhaps.

I mentioned DRAM because

* An FPGA could do it and the GA chips probably can't,

* You can't do a whole lot of embedded DSP apps without DRAM - it's not a question of "trying to be a PC", you just need memory to store stuff :-) and SRAM is too expensive.

Without DRAM, you're pretty much limited to what you call "streaming"; a whole lot of things don't work without being able to keep a working set in RAM. I don't argue that the chip is useless, just that it's useless in a huge range of use cases including many embedded ones, which is a sharp contrast to the connotations of its self-description as a "multi-computer chip"... And BTW even a really really dumb DSP chip can usually do DRAM :-)

I look at it as "an array of incredibly weak and energy-efficient cores" :-)