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X86 is a high-level language

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Re: X86 is a high-level language

#101

Earlier quoted context omitted.

The basic cause of a timing attack is that if cryptographic operations can take different amounts of time depending on the content, then we can potentially be leaking information to an attacker. If we try to solve this by padding our work using sleep() or similar, we might reveal less information directly – but the performance characteristics of our machine will still be different when we complete and operation quick…

I don't see it. I get what you're saying, but how does latency not swallow that difference? Or load balancing, or routing through the internal network behind the router. It's really hard for me to buy that an attacker can determine the execution characteristics of your crypographic functions via ping over the internet.

He/she said "ignoring loads of complexity". It was a gross oversimplification, but over thousands of trials it is possible to extract the information using a similar method.

Re: X86 is a high-level language

#102

Earlier quoted context omitted.

Can someone explain to me why you wouldn't just count clock ticks at a higher level than the CPU? If the operation finishes early just... wait. I understand resolution and yes you'll probably only be w/i a delta of some sort, but isn't that the point? Why wouldn't that approach work?

Your operating system hits memory pressure and pages your RAM page to disk. Some time later it restores it. Hey, look, you've suddenly had an arbitrarily long delay. So you can't always finish early. Also, even assuming you can always finish early, that plan won't prevent, for example, measuring the delay of other responses. (As your process sleeping will have an impact on how fast other responses are sent. Due to ca…

Why is it people can't ever respond to sanity, but instead assume idiocy?

You measure page faults in terms of milliseconds, I was not suggesting you even out the cryptographic timings to the tune of milliseconds, especially when you consider most cryptographic functions are setup specifically to take longer than that.

There is a delta that you can come up with such that things like page faults fall within it and it would still have acceptable performance. All but the most pounded of servers would be able to fall within it with no problem whatsoever.

Re: X86 is a high-level language

#103

Earlier quoted context omitted.

I don't see it. I get what you're saying, but how does latency not swallow that difference? Or load balancing, or routing through the internal network behind the router. It's really hard for me to buy that an attacker can determine the execution characteristics of your crypographic functions via ping over the internet.

He/she said "ignoring loads of complexity". It was a gross oversimplification, but over thousands of trials it is possible to extract the information using a similar method.

I'm interested in reality, not an oversimplification for academic reasoning. I thought that was clear.

Re: X86 is a high-level language

#104
post #29
post #19

Earlier quoted context omitted.

Any idea why the manufacturers haven't shown more interest in helping out crypto implementers? Surely timing attacks are a pretty prominent problem in microprocessor design circles by now.

Intel added AES, SHA-1 and SHA-256 instruction. They also added the PCLMULQDQ instruction to efficiently implement ECC. Via Padlock also have AES and SHA, and instructions for Montgomery multiplication (RSA speedup). Plenty of ARM SoC vendors offer crypto cores. So the toolbox to implement e.g. TLS securely is pretty much there. What isn't here is a way to implement new crypto primitives that would be timing attack a…

> They also added the PCLMULQDQ instruction to efficiently implement ECC.

Isn't this more typically used in GHASH implementations? Maybe it's applicable to both.

Re: X86 is a high-level language

#105

Earlier quoted context omitted.

I wrote the StackOverflow post, and I don't see anything in the article that points faulty assumptions. Don't get me wrong, I am glad that someone wrote that article. I was going to write a similar one myself within a few days with all the details I didn't need to expand on in the StackOverflow question because anyone who could answer didn't need them. If you see any specific assumption that the article points out as…

Have you checked to make sure that, for example, the kernel entry flag save / restore (i.e. PUSHFQ/POPFQ, etc.) doesn't take data-dependent time? Also, what about context switches in general? Stack memory can be zeroed to start. If you're writing zeros to the stack on a context switch I could see that being a different amount of time taken than if it's not zero. Due to the CPU not having to publish the memory write.…

> Have you checked to make sure that, for example, the kernel entry flag save / restore (i.e. PUSHFQ/POPFQ, etc.) doesn't take data-dependent time?

One only needs to trust the timings of instructions that one actually needs to implement cryptography. I admit I had not even considered whether an interruption and a visit through the scheduler could take an amount of time that depended of secrets; on some architectures it is possible to write code on purpose to leak secrets through this channel (a flag indicates whether multimedia registers are used, and these register, which can represent large amounts of memory to read and write, are only saved if they are used). But this is something developers would have to go out of their way to use. The implementation of cryptographic primitives should not require the flags to depend on secrets, so we can simply forbid this from happening rather than having to consider the execution times of all comparatively exotic instructions that handle the flags.

> If you're writing zeros to the stack on a context switch I could see that being a different amount of time taken than if it's not zero. Due to the CPU not having to publish the memory write.

Is this not the same question as the one in the StackOverflow question at http://stackoverflow.com/questions/29149058/does-memory-depe... ? I don't know, but someone who knows more about current micro-architectures than me thinks that instructions writing to memory takes the same execution times (see definition above) whether the value written is the same as the old value or not.

> It seems to me that all values that affect registers could potentially turn into a memory access.

You need to keep track of what register values depend on secrets. This is what ctgrind does. ctgrind warns when a register that has been computed from a secret is used for branching or memory access:

https://www.imperialviolet.org/2010/04/01/ctgrind.html

I made an equivalent version for C source (if you can separately convince yourself that your C compiler translates the C to assembler naively. This is another interesting question, but sometimes C source is what you have, so C source is what you need to verify)

http://blog.frama-c.com/index.php?post/2011/12/31/Do-not-use...

I have written a ton of articles on “C source code might not be translated to assembly that does what you think” and I have the trademark on that phrase, so please do not change the discussion to that of the compilation of C, it is a separate problem.

Ctgrind and Frama-C already work fine for symmetric cryptography, where they can help you check that the execution time does not depend on secrets simply by never using a secret in a branch or in the computation of an address of a memory access.

- that leaves the question of whether the time taken by the memory access can depend on the value being read. This is the StackOverflow question. Don't ask me, kidnap the family dogs of executives at Intel, AMD and ARM and get them to describe the current behavior of modern processors. Get them to make a few crucial promises for future processors while you're at it.

- it is not reasonable to constrain asymmetric cryptography to be implemented without memory accesses to addresses depending on secrets. The argument is going to need to be more subtle, saying that all possible secrets lead to the same instruction time. I am not sure how ctgrind could be adapted for this new challenge, but the good news is that Frama-C is very good at handling lots of possible values for variables and at computing program properties that hold for all these values.

Re: X86 is a high-level language

#106
post #80
post #73

Earlier quoted context omitted.

> You won't find data-dependent branches or look-ups in straightforward implementations of Curve25519 As it was pointed out already starting since Pentium 4, for example, the same assembly instruction "add dest, src" might take a different time depending on the value of dest and src. Unless those modern elliptic curve compensate for specific models of CPUs they run on, their straight C and assembly code might behave…

Are you talking about this paper? https://gmplib.org/~tege/x86-timing.pdf I only saw evidence of data-dependent timing with respect to the div operation, but maybe I missed something. Of course, I am not suggesting other operations are inherently immune to data-dependent timing leaks. EDIT: I see there are also some notes on adc and sbb in some situations, i.e. chains of instructions that all light up the carry flag.

Don't worry about the instruction, worry about dest, src. If they:

- Are in cache

- Were touched by a previous instruction (regardless of cache)

- Their cache line was touched by a previous instruction

- Will be read/write (immediately) after that instruction

- You're accessing data shared by multiple cores (lock prefix)

timing will vary

Re: X86 is a high-level language

#107

Earlier quoted context omitted.

What if, instead of a random sleep, you have a defined period of time for a function to take– you take a clock reading at the start and end of your execution, and sleep the remainder of the execution time?

The problem there is that sleeping alters the performance characteristics of your system. If an attacker submits multiple requests simultaneously, it would be possible for them to determine if you were actually working, or just sleeping - and you're back to leaking. Sure, every confounding factor makes it more difficult to extract information. But there are many effective techniques for doing so, and we keep getting…

A remote attacker is only able to measure total predetermined latency T = t_work + t_sleep. (Actually, he will measure T + t_noise [network, etc.]).

By what means can he determine which percentage of T+t_noise was spent in actual work?

Re: X86 is a high-level language

#108
post #29

Earlier quoted context omitted.

Intel added AES, SHA-1 and SHA-256 instruction. They also added the PCLMULQDQ instruction to efficiently implement ECC. Via Padlock also have AES and SHA, and instructions for Montgomery multiplication (RSA speedup). Plenty of ARM SoC vendors offer crypto cores. So the toolbox to implement e.g. TLS securely is pretty much there. What isn't here is a way to implement new crypto primitives that would be timing attack a…

> They also added the PCLMULQDQ instruction to efficiently implement ECC. Isn't this more typically used in GHASH implementations? Maybe it's applicable to both.

PCLMULQDQ is a godsend to both (GCM and binary elliptic curves), since both rely heavily on multiplication performance over F_{2^n}. The current fastest elliptic curve implementations are over binary fields using this instruction: http://eprint.iacr.org/2013/131.

Re: X86 is a high-level language

#109
post #36
post #20

Earlier quoted context omitted.

I think that's the author's point: x86 is now a significant abstraction from the actual details of execution.

That's true of all superscalar machines. That's what killed RISC. The original idea of RISC was one instruction per clock and a very simple CPU control section. Early MIPS CPUs realized that. Then superscalar came to microprocessors with the Pentium Pro. It took 3000 engineers at Intel to design that CPU, but it did much better than one instruction per clock while still handling all the weird cases in x86 instruction…

It's actually pretty straight forward to implement branch free RSA or ECC. Don't use Mod operations, use Montgomery Reduction or ECC curve specific reductions which are branch free.

Re: X86 is a high-level language

#110
post #36
post #20

Earlier quoted context omitted.

I think that's the author's point: x86 is now a significant abstraction from the actual details of execution.

That's true of all superscalar machines. That's what killed RISC. The original idea of RISC was one instruction per clock and a very simple CPU control section. Early MIPS CPUs realized that. Then superscalar came to microprocessors with the Pentium Pro. It took 3000 engineers at Intel to design that CPU, but it did much better than one instruction per clock while still handling all the weird cases in x86 instruction…

As a side note, the Pentium II was largely just the PPro with the parallel developed Pentium MMX's MMX instruction set also integrated into the core ISA (as opposed to being a separate execution unit like on the Pentium MMX), with a better bus and a smaller fab size (theres other small issues, but you only need to know about those if you're into writing kernels or writing compilers).
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