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How to Write Safe Verilog: Become a PL Troll

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Re: How to Write Safe Verilog: Become a PL Troll

#41

Post by VLM »

robomartin wrote: post #38

Being that HN is permeated by software developers it might be important to point out that Verilog code is not software but rather hardware description. The developer --in this case typically an EE-- either explicitly or through inference describes circuit structures with something that looks like a C-like programming language. Concepts such as modules don't translate directly into the software world. A module is a gr…

Three minor additions to what should become a HN FAQ every time there's a vaguely FPGA/ASIC article:

This is hardly official and not a perfect analogy but github is to software devs as opencores.org is to FPGA devs. Thats why when you go to github and search for Verilog and only get 259 hits for stuff written in Verilog you're going to the wrong place.

The other FAQ is verilog looks like C because C looks like the incredibly orthogonal PDP-11 addressing modes chart. So pretty much if you can imagine it as an addressing mode, the PDP-11 could do it, so thats explains the weird compatibility between something that looks like C and something that can define the hardware of a CPU. Its not a perfect analogy but it kind of describes why the HDL look very C like rather than Ruby like, for example. If you could build it out of basic logic gates in 1970 using TTL chips, its probably supported by the old PDP-11 and therefore in C.

Finally you need a FAQ for old timers that home-scale FPGA / CPLD stuff has collapsed in price over the last decade or two. Yes, in 1990 you needed four figures to do anything so no one did anything at home. Now you need at minimum a $50 board and a (multi-gig) free download. Its maybe 3dB more expensive than fooling around with arduino stuff. The small scale stuff doesn't scale well to larger stuff; I think its "weird" when a simple gray code decoder or quadrature decoder takes a minute to synth, so yes doing a complete CPU does take a long time to synth even on fairly high end hardware. Back to the old days of batch computing, sorta.

Re: How to Write Safe Verilog: Become a PL Troll

#42

Post by smilekzs »

iso-8859-1 wrote: post #34

Anyone who needs a Verilog with proper typing should check out Bluespec. It has the Haskell type system and it transpiles to Verilog. Due to type inference, it doesn't need to be verbose. Don't let my refernce to "Haskell" scare you, you decide yourself how general your code is. If you don't want to worry about monads, you don't need to.

His previous post mentioned that.

Re: How to Write Safe Verilog: Become a PL Troll

#43

Post by sliverstorm »

jnbiche wrote: post #33
sliverstorm wrote: post #16

Earlier quoted context omitted.

I don't remember what a BUF represents in FPGA tools- the name implies an inverter pair, e.g. buffer, but I don't remember for sure. Anyway, I mean a sequential element, such as a latch or a flip-flop. (If you don't know what those are, please pay a quick visit to Wikipedia- they are fundamental ) It is a placement/distance problem. Sometimes one module needs to talk to a module on the other side of the chip, and the…

I'm curious: you're discussing FPGAs with someone who knows enough about them to know the Xilinx instruction set. Why would you think that he/she might not know what a flip-flop is?

Because tcas thought when I said "latch" that I might meant "buf"

Re: How to Write Safe Verilog: Become a PL Troll

#44

Post by sliverstorm »

MichaelSalib wrote: post #37
aortega wrote: post #18

Earlier quoted context omitted.

Spent the last 2 years doing high-speed comm designs on FPGAs. (I don't know if 5 Gbps currently count as high speed though). The tools are quite mature and will mostly prevent you from doing stupid things. Somewhere here I saw a comment saying that you must time your design taking in account the logic delay or will get weird errors, but that's impossible. The tool chain (both quartus and Xilinx ISE) will report the…

Neverd did any ASIC but I know they have about 10X the testing and simulation that FPGA have. My spouse designs CPUs for a major CPU manufacturer (you've used them). She is responsible for physical design for one tile (there are many tiles, each of which has other physical designers). Her single tile, by itself, is substantially larger than almost all ASIC designs in the world today. At that scale, most of the standa…

The third type after FPGA and ASIC, sometimes called "full custom". Related to ASIC, but distinct.

http://en.wikipedia.org/wiki/Full_custom

Re: How to Write Safe Verilog: Become a PL Troll

#45

Post by robomartin »

VLM wrote: post #41
robomartin wrote: post #38

Being that HN is permeated by software developers it might be important to point out that Verilog code is not software but rather hardware description. The developer --in this case typically an EE-- either explicitly or through inference describes circuit structures with something that looks like a C-like programming language. Concepts such as modules don't translate directly into the software world. A module is a gr…

Three minor additions to what should become a HN FAQ every time there's a vaguely FPGA/ASIC article: This is hardly official and not a perfect analogy but github is to software devs as opencores.org is to FPGA devs. Thats why when you go to github and search for Verilog and only get 259 hits for stuff written in Verilog you're going to the wrong place. The other FAQ is verilog looks like C because C looks like the in…

Over the years I've accumulated a pile of dev/reference boards. In my world you eventually have to migrate to application specific hardware. This is where it quickly leaves the home/hobby domain, the tools get more expensive and the required knowledge-base expands. I am mostly talking about the challenges of high speed design.

The minute you get into the hundreds of MHz and into GHz and thousand pin devices you've entered a domain that is far away from what casual hackers can handle.

Yet, I do agree with you. Today, free compilers from Xilinx and Altera support devices that ten years ago required their multi-thousand dollar suites. Free or low-cost PCB design tools are out there. All of this of course, comes with compromises. Free simulation tools don't compare to paid tools. Free and low cost EDA software packages don't have all the tools you really need to efficiently manage high speed design of complex boards with larger devices. Signal integrity alone has dedicated (and very expensive) tools that you almost can't do without in certain domains.

None of this is to say that it is impossible for someone to play with the technology but it certainly ain't like playing with software.

Re: How to Write Safe Verilog: Become a PL Troll

#46

Post by robomartin »

thesz wrote: post #35
NoodleIncident wrote: post #2

This is a fascinating glimpse into a world I know less than nothing about. I don't anticipate ever needing to code in Verilog, but I'll try to keep this in mind and look for other places where a little effort can save a lot of time. I wonder what this has to say about type systems in general. Projects like Clojure's core.typed let you add static typing as a library where you feel like you need it, but then you don't…

Hardware programming is THE area where you need static types always on . Basically, you have to write everything in goto statements, no while's or for's. You also have to check that size always match, otherwise you will have errors. You also have to check that you do not accidentally drive one input from two outputs, otherwise you will also get errors. As you discover errors through very slow simulation (small circui…

> Hardware programming is THE area where you need static types always on.

It's not "hardware programming". It's hardware design. It's no different from connecting raw gates and chips on a breadboard. This is a very important distinction that is often glossed-over in HN conversations.

Verilog is a tool with which you explicitly or by inference DESCRIBE hardware. You are not programming hardware. That's software.

At some level this concept of static types is nonsensical. You have registers made up of flip-flops that move data around from circuit block to circuit block. That's it. Data types, in many ways, are software constructs, they don't really exist in hardware.

One would not look at a breadboard full of chips or an old-school PCB with latch and flip-flop chips and discuss static data types. Maybe you'll talk about fixed with data busses that implement this or that encoding, but that's about it.

One could argue that a specialized floating point processor has a data type. That's one way to interpret it. Another way is to say that it has a, say, 64 bit architecture that, by convention, is interpreted in order to be able to represent floating point numbers within certain constraints. If by that we mean "static data type" then, well, I suppose I can go with that.

Re: How to Write Safe Verilog: Become a PL Troll

#47

Post by VLM »

robomartin wrote: post #45
VLM wrote: post #41

Earlier quoted context omitted.

Three minor additions to what should become a HN FAQ every time there's a vaguely FPGA/ASIC article: This is hardly official and not a perfect analogy but github is to software devs as opencores.org is to FPGA devs. Thats why when you go to github and search for Verilog and only get 259 hits for stuff written in Verilog you're going to the wrong place. The other FAQ is verilog looks like C because C looks like the in…

Over the years I've accumulated a pile of dev/reference boards. In my world you eventually have to migrate to application specific hardware. This is where it quickly leaves the home/hobby domain, the tools get more expensive and the required knowledge-base expands. I am mostly talking about the challenges of high speed design. The minute you get into the hundreds of MHz and into GHz and thousand pin devices you've en…

Yes good point. Probably add another one to the standard HN FPGA FAQ that doing / learning X at home is pretty easy, as long as its not prefixed by "GHz" or "really fast".

Re: How to Write Safe Verilog: Become a PL Troll

#48

Post by robomartin »

StringyBob wrote: post #27
azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

I use these types of software day to day. The true price is veiled behind multi milkion dollar contract negotiations. You should see the inverse relationship between price and lack of bugs. What's more of a challenge is trying to use techniques like continuous integration when your compile time is a week!

> What's more of a challenge is trying to use techniques like continuous integration when your compile time is a week!

And your simulation time is another week.

And interpreting the results could be another week.

I've worked on designs where you can only do one iteration per day to on iteration per week. It really slows down development to a crawl.

You learn very quickly to segment designs and validate everything as far as humanly possible before even dreaming of simulating/compiling larger functional blocks.

These are ways in which modern hardware design is vastly different and vastly more expensive than any comparable software development workflow.

The cost of hardware tools is pretty much insignificant when you consider the entire process. Buying a $50,000 signal analyzer might save you weeks or months of development and debug time. You can't launch into these kinds of startups with a $15K investment over a summer.

Re: How to Write Safe Verilog: Become a PL Troll

#49

Post by StringyBob »

rcfox wrote: post #11
sliverstorm wrote: post #5

Earlier quoted context omitted.

How else are you supposed to get I/O... I believe the answer in this case is you latch the signal, and use a local copy. Sort of like how it is good practice to use local variables when coding. what's the definition of high speed Last I heard, 100MHz+

Just to clarify a bit: It takes time to go through combinational logic (AND and OR gates, etc.) and your clock has to go as slow as the slowest path to ensure that the signals are all correct at the same time. Registers are the start- and end-points of a combinational path, so placing a register in the critical path can increase your clock speed. However, that means that the data isn't available on the other side of…

Yes - Static Timing Analysis is used to work out worst likely timing (slowest/fastest delay) paths and check it runs at your target MHz

For ASIC work there are a couple of tools used these days: http://www.cadence.com/products/mfg/tempus/pages/default.asp...

http://www.synopsys.com/Tools/Implementation/SignOff/Pages/P...

Electronic Design Automation is a tough market to crack - for most startups the exit strategy is to be bought by one of the 2 (or 3) big players without being sued by them first!

Re: How to Write Safe Verilog: Become a PL Troll

#50

Post by nkurz »

jacquesm wrote: post #25
azernik wrote: post #24

Earlier quoted context omitted.

Oh, that wasn't a personal complaint - I'm not in the field, and don't know enough about it to roll my own. I'm more curious how this is sustainable as a business model, and how buyers of this software react to this kind of restriction.

That's because buyers do not generally see it as a restriction. The world you're referring to is not 'virtual', it is solidly grounded in capital goods for production. At the costs of a typical spin the use of the software is a very very small fraction, and that fraction is gladly paid because it avoids unnecessary spins (think of a spin as an 'edit-compile-test' cycle, only with a price tag of a few hundred K on the…

I appreciate your perspective, but I have great trouble getting past the feeling that this system is woefully societally inefficient. It seems so wasteful to have a handful of companies, each putting in tens of thousands of hours for products that do essentially the same thing, striving for lock-in and barrier to entry.

Yes, this is better than requiring each hardware company develop their own. But maybe there are other solutions that still result in the tools being available, both to those who can currently afford it and to those who can't? A shorter copyright term seems like one step in that direction. Nationalize one of the firms and open source it, leading to both a lower priced alternative and greater price competition for the remaining?

I guess it's a question of what the goal is. I'd put global accessibility to the developed technology up very high, and presume that dropping the cost and barriers to entry for both the hardware and software firms would help this.

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