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How to Write Safe Verilog: Become a PL Troll

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Re: How to Write Safe Verilog: Become a PL Troll

#21

Post by sliverstorm »

aortega wrote: post #18
tcas wrote: post #3

"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.

Spent the last 2 years doing high-speed comm designs on FPGAs. (I don't know if 5 Gbps currently count as high speed though). The tools are quite mature and will mostly prevent you from doing stupid things. Somewhere here I saw a comment saying that you must time your design taking in account the logic delay or will get weird errors, but that's impossible. The tool chain (both quartus and Xilinx ISE) will report the…

I would believe you don't get random errors if you follow the standard design flow and tests

In ASIC, or FPGA? With FPGA, you're probably right. With ASIC, it will depend on your goals. For example, I'm not aware of an industry standard methodology for accounting for the timing impact of localized supply droop. I believe that's something you have to cook up yourself.

Re: How to Write Safe Verilog: Become a PL Troll

#22

Post by azernik » 

  EDA tools vary in license costs, from a few thousand
  dollars per machine license per year, to half a million
  per core license per year. Timing tools aren’t all the way
  at the top end, but they’re not cheap.
I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is computationally expensive, but because licensing is too expensive in cash terms. Given the zero marginal costs (to software vendors) of existing customers running extra copies, this sounds completely insane to me.

Re: How to Write Safe Verilog: Become a PL Troll

#23

Post by jacquesm »

azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

You're entirely free to roll your own and to open source it.

Re: How to Write Safe Verilog: Become a PL Troll

#24

Post by azernik »

jacquesm wrote: post #23
azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

You're entirely free to roll your own and to open source it.

Oh, that wasn't a personal complaint - I'm not in the field, and don't know enough about it to roll my own. I'm more curious how this is sustainable as a business model, and how buyers of this software react to this kind of restriction.

Re: How to Write Safe Verilog: Become a PL Troll

#25

Post by jacquesm »

azernik wrote: post #24
jacquesm wrote: post #23

Earlier quoted context omitted.

You're entirely free to roll your own and to open source it.

Oh, that wasn't a personal complaint - I'm not in the field, and don't know enough about it to roll my own. I'm more curious how this is sustainable as a business model, and how buyers of this software react to this kind of restriction.

That's because buyers do not generally see it as a restriction.

The world you're referring to is not 'virtual', it is solidly grounded in capital goods for production. At the costs of a typical spin the use of the software is a very very small fraction, and that fraction is gladly paid because it avoids unnecessary spins (think of a spin as an 'edit-compile-test' cycle, only with a price tag of a few hundred K on the low end to a few million and up on the high end).

The software you're talking about has 1000's of manyears and sometimes 10's of thousands or even higher numbers of manyears involved in writing, testing, debugging. The present day value of that investment is so large that it serves as a defensible moat against any upstart company entering the market with a competing product, and if they do they will likely end up pricing it the same or higher (once they have the bugs worked out...).

Open source works well for fields where there are 100's of thousands of potential users for something that you can build in a reasonable amount of time and which does not require extensive domain knowledge spread out over lots of individuals.

For software like this, specialized, very expensive to develop and with a limited audience licenses are still the way it is done and as far as I can see it's the only model that makes sense. The alternative, bespoke software would be far more expensive still, the licenses are at least affordable to those who need them.

Re: How to Write Safe Verilog: Become a PL Troll

#26

Post by josteink »

azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

In my experience, software tailored for specific industries, sciences and academia, the electronics industry specificly, typically have prices in this range.

The narrower the field and harder the science, the fewer (and more expensive) candidates will be sufficiently competent to implement the software and the lesser audience for the software-publisher to recoup their RnD investment with, so prices tends to go up.

Once you need software to support engineering-disciplines not software, they know you will be able to pay the bill and find the software worthwhile compared to doing the same work manually with expensive engineers.

Re: How to Write Safe Verilog: Become a PL Troll

#27

Post by StringyBob »

azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

I use these types of software day to day. The true price is veiled behind multi milkion dollar contract negotiations. You should see the inverse relationship between price and lack of bugs.

What's more of a challenge is trying to use techniques like continuous integration when your compile time is a week!

Re: How to Write Safe Verilog: Become a PL Troll

#28

Post by pjc50 »

azernik wrote: post #22

EDA tools vary in license costs, from a few thousand dollars per machine license per year, to half a million per core license per year. Timing tools aren’t all the way at the top end, but they’re not cheap. I have never in my life touched software this expensive. It's interesting to me how this warps workflows - e.g. automated testing tools can only test one build every two days, not because running in parallel is co…

It's nothing at all to do with the marginal cost and all to do with extracting marginal _value_ from your tiny customer base with a high cost of sales.

I worked in an EDA startup for a decade before we were bought by Cadence. Getting people to evaluate our tool generally took a few months of a technical presales person's time. We only ever acquired a few dozen customers: there aren't all that many ASIC companies. Most required at least one custom feature. Therefore there's an elaborate commercial negotiation to take as much money as possible from the customer in order to amortize the R&D.

Given manufacturing fixed costs of $250k, spending $250k on software to get it right starts to look reasonable.

Re: How to Write Safe Verilog: Become a PL Troll

#29

Post by pjc50 »

jacquesm wrote: post #25
azernik wrote: post #24

Earlier quoted context omitted.

Oh, that wasn't a personal complaint - I'm not in the field, and don't know enough about it to roll my own. I'm more curious how this is sustainable as a business model, and how buyers of this software react to this kind of restriction.

That's because buyers do not generally see it as a restriction. The world you're referring to is not 'virtual', it is solidly grounded in capital goods for production. At the costs of a typical spin the use of the software is a very very small fraction, and that fraction is gladly paid because it avoids unnecessary spins (think of a spin as an 'edit-compile-test' cycle, only with a price tag of a few hundred K on the…

I agree; market entry to EDA, even for a "utility" that you add to the build chain to improve your results, is extremely hard.

Re: How to Write Safe Verilog: Become a PL Troll

#30

Post by DigitalJack »

sliverstorm wrote: post #7
CamperBob2 wrote: post #4

Earlier quoted context omitted.

To some extent his advice suffers from the same problem that many books suffer from, in that it comes from the ASIC world while a large share of Verilog work these days is probably done to target FPGAs. For reasons too long to elaborate upon here, you can get away with a lot of things on FPGAs that may not be such a good idea on ASICs.

you can get away with a lot of things on FPGAs... Perhaps the most important thing you can get away with? Errors. Reprogramming an FPGA takes three minutes; manufacturing a new ASIC takes three months and three million dollars (or something along those lines). So dot your i's and cross your t's, baby.

True for some FPGAs. anti fuse still has a place in the industry.
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