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Why hardware development is hard: Verilog is weird

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Re: Why hardware development is hard: Verilog is weird

#41
> not because of deficiencies in [Haskell], but because it’s politically difficult to get people to use a Haskell based language

I know tons of languages, but I've never really been able to understand Haskell. The whole monad thing is just...weird. I've read several descriptions, and had it explained to me multiple times on HN, but I still just Don't Get It. And I feel like I should Get It, because I have a degree in math including an upper-level course in logic.

To me, that suggests a problem with the language design of Haskell -- maybe monads are a bad abstraction, maybe the syntax should be different, maybe there's a brilliant and simple explanation that I haven't found yet. But the bottom line is that the learning curve for people coming from other languages needs to be a lot lower for Haskell to ever be anything but a tiny niche.

Re: Why hardware development is hard: Verilog is weird

#42

Earlier quoted context omitted.

given how difficult hardware synthesis with existing HDLs is right now I don't know if that'll happen anytime soon Synthesis sometimes feels like a great blind spot in the hierarchy of abstractions. It is hard, critical, and yet appears to be developed only by niche players. the fact that logic takes so long to synthesize and simulate really has little to do with Verilog's deficiencies IMO it has everything to do wit…

I think the issue here is that Synthesis and Place and Route tools are squarely in the Computer Science Algorithms domain. Hardware engineers in general don't have the background for that kind of work. And software engineers don't crossover to the hardware side often. So the people suffering with the "slow" tools etc, are usually not in a very good position to do anything about it. But really, the slow side is in the…

On the bright side, route is pretty strongly parallelizable. So even if it takes the most CPU time, it doesn't have to be the long pole.

Re: Why hardware development is hard: Verilog is weird

#43

So um, why do they hate Haskell? "it's politically difficult", "scary", "one person suggested banning any Haskell based solution" Just going by his description (as I don't know much about hardware design except a single uni course ~15 years ago), it sounds as if a functional programming language like Haskell would be a perfect fit? "one person suggested banning any Haskell based solution" -- that's pretty much litera…

Functional programming doesn't make sense for this sort of thing as you can't define a circuit recursively. Mitrion-C is an example of a higher-level functional language aimed at configuring FPGAs. It's pretty useless unless you have insider knowledge on how the system works.

Synchronous data-flow programming is a functional style language made for programming embedded systems. It follows the paradigm of clocked circuits, where variables are wires.

Check for example Lustre/Scade: http://www.esterel-technologies.com/ or its more recent successor Lucid synchrone: http://www.di.ens.fr/~pouzet/lucid-synchrone/

The latter has explicit recursion which can be disabled when designing embedded systems.

Haskell libraries closely follow this paradigm with their functional reactive DSLs. Recursion is actually useful to recursively define circuits with repeated patterns, e.g., the butterfly FFT.

Re: Why hardware development is hard: Verilog is weird

#44
post #5

Cyclicity CDL is nice: http://cyclicity-cdl.sourceforge.net/cdl.php

I'd also like to point out MyHDL: http://www.myhdl.org/doku.php It allows the full power of Python (being just another module) while you're developing and testing, and when you're ready to compile to hardware you can compile the RTL subset of your program to Verilog or VHDL and take it to hardware from there. The creator did a good talk about it at PyCon Taiwan earlier this year: http://www.youtube.com/watch?v=LSgOpv…

MyHDL is great, more people should use it. I find it especially powerful for building test frameworks. I love using the power of Python for all the verification logic.

Re: Why hardware development is hard: Verilog is weird

#45

Something seems off to me about this post. One generally simulates the RTL long before doing anything with gates. Mostly because RTL is faster. Only when you have things sufficiently nailed down, have done all the timing analaysis, etc, do you start running gate sims. Even for pretty damn large designs, compiling RTL shouldn't be a big hinderance…minutes instead of hours. Considering the magnitude of complexity invol…

VCS took 15 minutes for SV recompile and 60+ for clean compile (depending on level of "clean" and level of "compile") for "large" projects on top of the line servers.

Re: Why hardware development is hard: Verilog is weird

#47
post #41

> not because of deficiencies in [Haskell], but because it’s politically difficult to get people to use a Haskell based language I know tons of languages, but I've never really been able to understand Haskell. The whole monad thing is just...weird. I've read several descriptions, and had it explained to me multiple times on HN, but I still just Don't Get It. And I feel like I should Get It, because I have a degree in…

There isn't much to Monads at all. One problem that some Haskell beginners hit is that they read some bunk monad explanations and only get confused, and that monads get so hyped up that when met with the actual description, they try to look for something more that isn't actually there.

Monads are just a set two or three operations on a data structure, which obey certain laws. The operations are either ( map(function,structure), collapse(structure), create(value) ) or ( bind(function,structure), create(value) ) where you can implement map and collapse in terms of bind, and vice versa. You don't even need to know the laws to use monads, only to create a new monad.

map(function,structure) is a function that applies a function to every element in the structure. Pretty straightforward. For example:

    -> map(addThree,[1,2,3])
    [4,5,6]
Collapse is a function which takes structures embedded in a structure of the same type, and gets rid of one level. For lists, it's the same as concatenating all sublists.

    -> collapse([[],[3,4],[6,1,2]])
    [3,4,6,1,2]
Create takes a value and puts it into the structure in the simplest way possible.

    -> create(3)
    [3]
These three functions are enough to have a monad over your structure, and are how monads are usually defined in mathematics. But lets look at the alternative.

For the sake of explaining bind, let's introduce a new function which we will just use as an example:

    -> func makeThree(value): return [value,value+1,value+2]
Let's say we have a list of values [3,1,5] and we want to apply makeThree on it to get a new list. Let's try doing it using map.

    -> map(makeThree,[3,1,5])
    [[3,4,5],[1,2,3],[5,6,7]]
We got a list of lists rather than just the simple list we wanted, but we can use collapse to get it into what we want:

    -> collapse(map(makeThree,[3,1,5]))
    [3,4,5,1,2,3,5,6,7]
And here is an example of using bind to do the same thing:

    -> func bind(function,structure): return collapse(map(function,structure))
    -> bind(makeThree,[3,1,5])
    [3,4,5,1,2,3,5,6,7]
This definition of bind is valid for all monads. I have used the list monad as an example here, but many other structures are also monads. You don't really see the power of what you can really do with monads until you use them in a language that supports them well. In the actual definition of monads, collapse is called join. The definition using bind is the one that is more popular in programming, while the definition using join and map is more popular in mathematics.

I'm not actually going to show what the laws governing the interactions between these functions are in this comment, but I can explain them if you ask.

Re: Why hardware development is hard: Verilog is weird

#48
post #6
post #2

The problem is that Verilog/VHDL isn't a "programming language" in the sense that C, Lisp, Haskell, or Python are programming languages. So approaching them with a programming language mindset is asking for a lot of pain and misunderstanding. HDLs like Verilog and VHDL describe digital circuits, not algorithms and instructions for manipulating data. If C code is akin to instructions for getting to a grocery store and…

The author touches on this, when he says: "To write Verilog that will produce correct hardware, you have to first picture the hardware you want to produce." I think that's the crux of the issue. Most digital designers do have a picture of the actual hardware, as a block diagram, in their heads. When I write RTL, the process is very front-loaded: I spend hours with a pen and paper before I even sit down at the keyboar…

>> if "why's it taking so long?" is a question that interests you, I recommend looking into the VLSI CAD tools class on Coursera.

Could you please provide a summary? I know optimization is hard and thereby slow. But is that why? Thanks.

Re: Why hardware development is hard: Verilog is weird

#49
LOL, I love this thread. Hardware is the new Software! But Hardware description languages are just that, structured languages that describe hardware. If you come from a background of programming, it will be hard for you. I am someone who comes from a background of hardware that had to learn software, but then when Verilog came along, oh man, was I in heaven. Do not think of VHDL or Verilog as a language, think of it more in terms of HTML, HTML is a mark up language for type setting, HDL is a mark up language for hardware. Hardware is not sequential, everything will happen at the same time unless you prevent that with a state machine. With sequential languages like C or Pascal etc., everything happens sequentially unless you go out of you want to try to make things happen seemingly at once. With HDL, you have the opposite problem, everything will happen at once on each clock cycle, unless you make a state maching to make things sequential. Once you see this, and the amazing power of it, you will see why I say... Hardware is the next Software.

Re: Why hardware development is hard: Verilog is weird

#50
post #41

> not because of deficiencies in [Haskell], but because it’s politically difficult to get people to use a Haskell based language I know tons of languages, but I've never really been able to understand Haskell. The whole monad thing is just...weird. I've read several descriptions, and had it explained to me multiple times on HN, but I still just Don't Get It. And I feel like I should Get It, because I have a degree in…

There isn't much to Monads at all. One problem that some Haskell beginners hit is that they read some bunk monad explanations and only get confused, and that monads get so hyped up that when met with the actual description, they try to look for something more that isn't actually there. Monads are just a set two or three operations on a data structure, which obey certain laws. The operations are either ( map(function,…

TDIL, thanks!
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