Latest Shipment of Avalon ASICs Could Increase Network Hashrate By 500%

Post by ohazi » Fri, Jul 12, 2013, 1:28 AM UTC

aristidb wrote: post #28

zanny wrote: post #24

Earlier quoted context omitted.

You do realize the whole premise of an application-specific-integrated-circuit is to do one thing the best. If properly architected, an ASIC that does the most SHA hashing with the least transistors will be the best miner, inherent to the technology.

That doesn't mean the designs cannot be improved... And once somebody releases an improved design, the older ASICs become far less useful.

Post by [deleted] » Fri, Jul 12, 2013, 1:53 AM UTC

ohazi wrote: post #41

aristidb wrote: post #28

Earlier quoted context omitted.

That doesn't mean the designs cannot be improved... And once somebody releases an improved design, the older ASICs become far less useful.

At this point, an "improved" design would have to mean algorithmic improvements to a hardware SHA algorithm (i.e. not likely). Improvements that you can actually count on would be die shrinks, but these will provide returns in accordance with the tail end of Moore's law. Compared to the multiple-order-of-magnitude improvements from the CPU -> GPU/FPGA -> ASIC jumps, these improvements likely won't even be worth writi…

Post by Aqua_Geek » Fri, Jul 12, 2013, 7:29 AM UTC

qwertzlcoatl wrote: post #37

And Butterfly Labs still hasn't shipped their orders from Day 1. There will be an awful lot of people who will never see a return on their investment from this venture.

Post by mrb » Fri, Jul 12, 2013, 8:56 PM UTC

kijiki wrote: post #44

mrb wrote: post #36

Earlier quoted context omitted.

There is no next step. ASIC is the end-all be-all. (Not even quantum computing can help - there is no known algorithm to help find SHA256 preimages, which is what would be necessary for a Bitcoin mining breakthrough.)

ASIC is the 2nd to last step. The next (final) step is a full custom design, co-developed with the fab process. This is how Intel & AMD design CPUs.