Earlier quoted context omitted.
Each of the 64 cores can independently run arbitrary C/C++ code, which is much more flexible than a GPU. Each core has 32KB of local memory, which can also be accessed by the other cores, and there's 1GB of external memory too. Specs: http://www.adapteva.com/products/silicon-devices/e64g401/ Architecture: http://www.adapteva.com/wp-content/uploads/2012/10/epiphany_... SDK docs: http://www.adapteva.com/wp-content/uplo…
Interesting architecture. I like how well-documented everything is. Usually, either the low-level ISA for accelerator chips is not documented at all (like with GPUs), or detailed documentation is only available under NDA, and only proprietary development tools are available (like with FPGAs). The topology reminds me of this paper "The Landscape of Parallel Computing Research: A View from Berkeley" http://www.eecs.ber…
Let me show you the AMD Southern Islands ISA specs: http://developer.amd.com/wordpress/media/2012/10/AMD_Souther...