Earlier quoted context omitted.
The 6502 is an interesting case. The decode ROM (PLA) gets instructions about 1/3 of the way decoded, and then there's a whole pile of random control logic [1], [2] that generates the actual control lines [3]. The output from the decode ROM consists of semi-meaningless things such as ADC/SBC in state T0, or JSR in T5 [4], and after a whole bunch of gates these get turned into the actual control functions such as S bu…
"Random control logic" Oxymoron? Is the control logic really random in some way? That sounds impossible. Or at least, very highly inefficient.
Google the expression to learn more.