Earlier quoted context omitted.
Every trace on a PCB is a traveling salesman problem with ballooning complexity. https://en.wikipedia.org/wiki/Travelling_salesman_problem While physics informed models do exist, they are still going to burn a lot of compute to generate failure modes people didn't know were possible. =3 https://www.youtube.com/watch?v=T4Upf_B9RLQ
Well, no, it's not. If anything, it's closer to the bin packing problem. The cost function isn't expressed in terms of lowest cost between nodes, but instead fitting all of the traces with the lowest board layer count while still meeting stuff like EMI crosstalk guidelines. Then there'll be some traces that are very constrained (think DRAM or SERDES links) that have to be length matched, but those are pretty much inv…
Impedance matching requires you know what you are doing, and Altium will only take you so far. For the price, Altium/Protel has always been a poor deal for what you get software wise.
Even free Qspice (a more modern Analog Devices LTSpice) is a far better option:
https://www.qorvo.com/design-hub/calculators-simulation/qspi...
>the industry doesn't look for optimal, only good enough
Indeed, that is why your iPhone still weighs 3.7 kg. =3