Earlier quoted context omitted.
I've started to dabble in this only very recently. I have two iCEBreaker boards [0] in the mail right now that I'm excited for. From what I understand, one of the big advantages of the up5k chip (the same chip on the webfpga and the icebreaker) is that there's an open toolchain that runs in seconds (at this chip size), which is not the case in the closed/Vivado/"typical fpga" part of the world. (feel free to correct…
A trick to fit language models of this size it to remove the word to embeddings from the NN, and have a database to look up a dictionary of words and their embeddings. This way the LLL only need the "core" and you do the reverse for loopup again (kind of Text->RAG->LLM->RAG->Text). Have an example here: https://punnerud.github.io/pyspell/ The example have a limited language of around 1000 words, but make it possible…
re: language model - here, the embedding lookup, layers, logits all run on-chip and loops its own output back.
the only off-chip piece is the id to string table, i.e. the chip (once I get it!) will speak token ids and my laptop will print them as letters