Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

RISC-V is now officially supported by CPython

blog.python.org

Post reply on HN
Print view View original

61–70 of 76 posts

Re: RISC-V is now officially supported by CPython

#61

Post by jubilanti »

6SixTy wrote: post #59
jubilanti wrote: post #57

Earlier quoted context omitted.

So is 32bit out of scope? ESP32 devices are increasingly RISC-V but 32bit.

32 bit RISC-V is pretty much limited to microcontrollers. There's no serious projects to create a Linux capable RV32 machine. Only FPGA soft cores and QEMU. There is micropython, but just from the description, it's a separate project entirely with the same syntax, etc.

> 32 bit RISC-V is pretty much limited to microcontrollers

Hence me explicitly talking about ESP32. I was asking about microcontrollers. I know about micropython. I was asking about CPython.

Re: RISC-V is now officially supported by CPython

#62

Post by gavinsyancey »

jubilanti wrote: post #61
6SixTy wrote: post #59

Earlier quoted context omitted.

32 bit RISC-V is pretty much limited to microcontrollers. There's no serious projects to create a Linux capable RV32 machine. Only FPGA soft cores and QEMU. There is micropython, but just from the description, it's a separate project entirely with the same syntax, etc.

> 32 bit RISC-V is pretty much limited to microcontrollers Hence me explicitly talking about ESP32. I was asking about microcontrollers. I know about micropython. I was asking about CPython.

CPython needs you to also be running an operating system. And while it might be theoretically possible to get a NoMMU Linux running on an ESP32, that's generally not very useful for practical applications compared to micropython or something that's actually designed for a microcontroller.

Re: RISC-V is now officially supported by CPython

#63

Post by hajile »

shash wrote: post #52
ironhaven wrote: post #11

What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against. It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance wi…

It’s not like GC isn’t a massive part of RVA23 - those are the basic instructions that handle 80-90% of all uses (including most of what CPython needs). I’m sure one could do some optimizations on RVA23, but is it really worth it?

Vectors are pretty big for speeding up stuff like string comparisons.

Bit manipulation offers up to almost 10% advantage.

Zicond allows branchless code which represents significant speedups.

There’s also serious gains to be had from crypto support.

I’d guess the rest aren’t as important to Python, but those are quite important.

Re: RISC-V is now officially supported by CPython

#64

Post by ccgreg »

Marcuss2 wrote: post #45
ccgreg wrote: post #39

Earlier quoted context omitted.

How is this different from x86_64 and aarch64? Or even the various Alpha and Mips64 chips.

For example x86_64 has v1, v2, v3 and v4 baselines, this tells you which instructions they support (e.g. v4 has AVX-512, v3 has AVX2, etc.). RISC-V RVA22 and RVA23 aren't too different in this regard. Each one prescribes which extensions must be supported by the processor. I saw RV64GC mentioned, this is just a shortening of RV64IMAFDC, so I for baseline instructions, M for multiplication and division, A for atomic,…

Another aspect of the x86_64 architectural swamp is that Intel deliberately makes their optimized math libraries fail if run on a chip that is not 'INTEL INSIDE'. That block totally ignores cpu feature bits.

I've always wondered if virtualization software vendors made everything claim to be INTEL INSIDE, just to avoid this problem.

Re: RISC-V is now officially supported by CPython

#65

Post by bonzini »

ccgreg wrote: post #64
Marcuss2 wrote: post #45

Earlier quoted context omitted.

For example x86_64 has v1, v2, v3 and v4 baselines, this tells you which instructions they support (e.g. v4 has AVX-512, v3 has AVX2, etc.). RISC-V RVA22 and RVA23 aren't too different in this regard. Each one prescribes which extensions must be supported by the processor. I saw RV64GC mentioned, this is just a shortening of RV64IMAFDC, so I for baseline instructions, M for multiplication and division, A for atomic,…

Another aspect of the x86_64 architectural swamp is that Intel deliberately makes their optimized math libraries fail if run on a chip that is not 'INTEL INSIDE'. That block totally ignores cpu feature bits. I've always wondered if virtualization software vendors made everything claim to be INTEL INSIDE, just to avoid this problem.

Nope, there are subtle differences between Intel and AMD that make it a Bad Idea to fake the vendor.

Re: RISC-V is now officially supported by CPython

#67

Post by ccgreg »

bonzini wrote: post #65
ccgreg wrote: post #64

Earlier quoted context omitted.

Another aspect of the x86_64 architectural swamp is that Intel deliberately makes their optimized math libraries fail if run on a chip that is not 'INTEL INSIDE'. That block totally ignores cpu feature bits. I've always wondered if virtualization software vendors made everything claim to be INTEL INSIDE, just to avoid this problem.

Nope, there are subtle differences between Intel and AMD that make it a Bad Idea to fake the vendor.

There are? We aren't talking about feature bits, and the only known software that checks the vendor are Intel's math libraries.

Re: RISC-V is now officially supported by CPython

#68

Post by greatgib »

boredatoms wrote: post #50
greatgib wrote: post #22

For quite some times I'm wondering how I could invest in RISC, or RISC related manufacturer but it looks like all companies are private.

Check out Hiive and make a bid if you want Sifive stock also Andes is public

Sadly I think that Hiive is restricted to US based investors.

Re: RISC-V is now officially supported by CPython

#70

Post by jdc-pub »

Marcuss2 wrote: post #45
ccgreg wrote: post #39

Earlier quoted context omitted.

How is this different from x86_64 and aarch64? Or even the various Alpha and Mips64 chips.

For example x86_64 has v1, v2, v3 and v4 baselines, this tells you which instructions they support (e.g. v4 has AVX-512, v3 has AVX2, etc.). RISC-V RVA22 and RVA23 aren't too different in this regard. Each one prescribes which extensions must be supported by the processor. I saw RV64GC mentioned, this is just a shortening of RV64IMAFDC, so I for baseline instructions, M for multiplication and division, A for atomic,…

Huh, where does the “G” come from in RV64GC?
Post reply on HN