[flagged]
How is Python a dead language due to ML when it's the lingua franca of AI/ML between pytorch, pandas, numpy, langchain, litellm, vLLM, and a whole bunch of other libraries?
Unison.
RISC-V is now officially supported by CPython
21–30 of 76 posts
Re: RISC-V is now officially supported by CPython
#22For quite some times I'm wondering how I could invest in RISC, or RISC related manufacturer but it looks like all companies are private.
Re: RISC-V is now officially supported by CPython
#23Can we do something about CPython Global Interpreter Lock (GIL)?
Re: RISC-V is now officially supported by CPython
#24Can we do something about CPython Global Interpreter Lock (GIL)?
Free threaded Python - optional but supported
Re: RISC-V is now officially supported by CPython
#25Re: RISC-V is now officially supported by CPython
#26What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against. It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance wi…
I wonder how much this matters for python.
As long as the important dependencies like numpy runtime dispatch RVV, it should probably be fine.
Zba would probably give a small boost. Zbb gives a substantial boost to perf for applications that use clz/popc heavily, but I don't think that would apply to python.
Re: RISC-V is now officially supported by CPython
#27What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against. It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance wi…
RISC-V fragmentation bites again...
The same problem exists for x86. Is $program built for x86-64 with SSE2? AVX2? AVX512? (I chose those three because they are programmer-visible. Programmers have to use intrinsics to exploit those ISA extensions effectively.)
For RISC-V the questions to ask are similar: Is this built for RVA20? Or RVA23? (The big feature of RVA23 is the Vector extension, again something that is programmer-visible)
Embedded RISC-V programmers will have to ask a lot more questions. But for most programmers the whole fragmentation thing is simply a giant meme repeated ad nauseam.
Re: RISC-V is now officially supported by CPython
#28What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against. It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance wi…
RISC-V fragmentation bites again...
People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores.
On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512.
On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting.
At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point.
So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.
Re: RISC-V is now officially supported by CPython
#29Earlier quoted context omitted.
RISC-V fragmentation bites again...
People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores. On x86 situation is even crazier https…
For AP cores where Python actually runs it’s just “arm8” and pick your incremental version on top.
Re: RISC-V is now officially supported by CPython
#30CPython is written in C, did running it on Risc-V take more than a recompilation? Were there any surprises? Yes of course it needs testing and RISC-V in the CI stack, but I'd expect fairly smooth sailing.