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IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

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Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#111

Post by BillStrong »

sylware wrote: post #109
u1hcw9nx wrote: post #88

Not explained in the article: Every single physical core on the chip decodes and executes both s390x and Arm AArch64 instructions, dynamically switching between the two ISA modes and convert them into micro ops. Mode switching is hypervisor-driven. And those chips are fast. 5.7 Ghz 2nm node. For who: When you need to run Linux programs on high security, mission critical environment. Others should not care.

So why the 2nm x86 chips are clocked so low? Why couldn't they be 6GHz? x86_64 ISA did it again? That said IBM should add RISC-V support.

The AMD Zen 6 line is targeting 7GHz in the upcoming releases, on 2nm, so......

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#112

Post by sylware »

BillStrong wrote: post #111
sylware wrote: post #109

Earlier quoted context omitted.

So why the 2nm x86 chips are clocked so low? Why couldn't they be 6GHz? x86_64 ISA did it again? That said IBM should add RISC-V support.

The AMD Zen 6 line is targeting 7GHz in the upcoming releases, on 2nm, so......

Last time I read something about Zen6 it was 6GHz.

So I guess the IBM stuff is "server slow" then.

I wish RISC-V microarchitectures would get access to 2nm silicon processes, because RISC-V at 7GHz... yummy.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#113

Post by stinkbeetle »

jasomill wrote: post #91
stinkbeetle wrote: post #58

Earlier quoted context omitted.

ARM can emulate z workloads. https://hercules-390.github.io/html/index.html (or QEMU, for partition level emulation).

Sure. And you can run ARM workloads under QEMU on s390x Linux.

Sure. And you can run ARM workloads in hardware ARM mode.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#114

Post by bmitc »

dmitrygr wrote: post #64
bmitc wrote: post #62

Earlier quoted context omitted.

To my understanding, the RP2350 has two ARM cores and two RISC-V cores, the two pairs are separate, and only one architecture can be used at a time on the chip.

nope. two "slots", each selectable from {ARM, RISCV}. In each, you pick one. so you can configure it at two arm cores, arm + riscv, or two riscv cores. dual-arch is possible, if you desire it

Thanks, and yea, you're right. Their top-level copy muddies the waters on this and makes it sound like what I wrote, but indeed, from their datasheet:

> The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.

> Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for example.

> Hardware supports debugging for a mixture of Arm and RISC-V processors, though this may prove challenging on the host software side. Debug resources for unused processors are dynamically marked as non-PRESENT in the top-level CoreSight ROM table.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#115

Post by bobmcnamara »

userbinator wrote: post #87

The article is quite short on details but I wonder if this is an ARM core that can also execute IBM Z, or the other way around; in other words, which ISA does it execute its first instruction at the reset vector? In that past I've worked on a conceptual design for an "x86+" CPU, which would start as a regular x86 but then be able to execute code of other architectures like ARM, MIPS, PPC, etc. isolated in their own c…

Old Arm did something similar where you could transition between thumb and arm instruction sets dynamically.

Looks like this one you choose the ISA per process? Per VM?

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#116

Post by bryanlarsen »

trwei wrote: post #73
christkv wrote: post #26

Earlier quoted context omitted.

I wonder how they handle potential differences in memory barriers, instruction order scheduling and other stuff and do they run the core in one mode continuously or do the mix instruction streams from different instruction sets? Anybody got a link to an article?

Z’s memory model is much stronger than arm, so running arm on z memory model requires almost no design changes. The inverse is not true.

Which leaves a substantial amount of performance on the table. Which IBM may be fine with, but benchmarks are important to IBM.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#117

Post by dfox »

userbinator wrote: post #87

The article is quite short on details but I wonder if this is an ARM core that can also execute IBM Z, or the other way around; in other words, which ISA does it execute its first instruction at the reset vector? In that past I've worked on a conceptual design for an "x86+" CPU, which would start as a regular x86 but then be able to execute code of other architectures like ARM, MIPS, PPC, etc. isolated in their own c…

IBM's mainframes do not really have a reset vector, the CPU gets initialized by some external means into whatever state the OS expects and then the clock gets enabled, so that distinction is quite moot.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#118

Post by trollbridge »

_joel wrote: post #107
trollbridge wrote: post #106

Earlier quoted context omitted.

It’s a rebranding of ML which IBM has promoted for quite some time, used in a rather conventional fashion. AI does not always mean LLM.

I never said it did? ML has inference too, so...

Well, let's just say that Amex and Visa have been doing advanced fraud detection, using ML techniques, for years... and yes, some of that inside the z/TPF environment.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#119

Post by dfox »

rbanffy wrote: post #95
pezezin wrote: post #85

Earlier quoted context omitted.

I found this article with the diagram that you mention: https://wccftech.com/ibm-worlds-first-dual-architecture-proc... The diagram is the last picture, and according to it you choose the ISA at the VM level: either Linux on s390x or Linux on arm64, but not both on the same VM.

Interesting that z/VM doesn't seem to support spinning up ARM Linux VMs, at least according to this diagram, but it does support bringing up s390x Linux VMs (the LinuxONE Community Cloud creates Linux VMs under z/VM). Also, it looks like z/OS is running directly on the LPAR, which wasn't common the last time I looked (a decade ago, more or less).

I suspect that is not an inherent limitation of the dual-ISA design (the HotChips slides mention some sort of bidirectional thread state mapping between arm and z), but just about there not being z/VM release that supports that (building such a thing is probably SMoP, but another question is whether that makes business sense).

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#120

Post by kevin_thibedeau »

bobmcnamara wrote: post #115
userbinator wrote: post #87

The article is quite short on details but I wonder if this is an ARM core that can also execute IBM Z, or the other way around; in other words, which ISA does it execute its first instruction at the reset vector? In that past I've worked on a conceptual design for an "x86+" CPU, which would start as a regular x86 but then be able to execute code of other architectures like ARM, MIPS, PPC, etc. isolated in their own c…

Old Arm did something similar where you could transition between thumb and arm instruction sets dynamically. Looks like this one you choose the ISA per process? Per VM?

And Jazelle.
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