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IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

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Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#81

Post by bonzini »

rbanffy wrote: post #41
pulse7 wrote: post #15

Earlier quoted context omitted.

"code translation in hardware" microcode is called "native"

IBM’s microcode is really something. Not too long ago I heard about writing “millicode” as something that’s not at the microcode level, but not quite up at the ISA level.

Millicode used custom extensions to the ISA but is otherwise regular s390 code. For example there is a separate register file and the "original" registers are available with either (I don't remember exactly) special instructions or special memory addresses.

Intel by the way did the same for SGX, they called it xucode.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#83

Post by monocasa »

Melatonic wrote: post #70
monocasa wrote: post #44

Earlier quoted context omitted.

Yeah, their cache work is undeniably really cool. That being said I think it's a natural consequence of the difference between a mainframe and commodity servers. A mainframe is going to be running pretty disparate workloads simultaneously, so it makes sense to steal from your neighbor if they aren't using their cache. Whereas it's more likely that a commodity server is just running the same server on each core, and i…

What's unique about their cache ?

Basically for Telum II, (I don't know what changed here from Telum III, the core under discussion with the ARM decoders) each CPU core has a giant 36MB L2 cache. Then, rather than a discrete L3 cache, the cores keep track of L2 residency needed for that core's working set, and allocate the rest of their L2 to a shared pool that is the L3 cache. Then the same thing with L4 being the same pools in all of the other chips on the same drawer (which you can kind of think of as close to a single server).

https://chipsandcheese.com/p/telum-ii-at-hot-chips-2024-main...

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#84

Post by Melatonic »

monocasa wrote: post #83
Melatonic wrote: post #70

Earlier quoted context omitted.

What's unique about their cache ?

Basically for Telum II, (I don't know what changed here from Telum III, the core under discussion with the ARM decoders) each CPU core has a giant 36MB L2 cache. Then, rather than a discrete L3 cache, the cores keep track of L2 residency needed for that core's working set, and allocate the rest of their L2 to a shared pool that is the L3 cache. Then the same thing with L4 being the same pools in all of the other chip…

Wow that is a massive cache. Pretty cool. Guessing it would great for data throughput !

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#85

Post by pezezin »

rbanffy wrote: post #36
christkv wrote: post #26

Earlier quoted context omitted.

I wonder how they handle potential differences in memory barriers, instruction order scheduling and other stuff and do they run the core in one mode continuously or do the mix instruction streams from different instruction sets? Anybody got a link to an article?

Possible different micro ops for different semantics. They also don’t mix instructions sets within the same process - the diagram I saw had ARM Linux as a guest under z/VM or KVM. For generations now no OS (not VM, not z/OS) hasn’t seen the bare metal machine, only ran under the PR/SM hypervisor, which is what does the logical partitions now. In order to properly run OSs for the 360 and 370 generations, s390x also ha…

I found this article with the diagram that you mention: https://wccftech.com/ibm-worlds-first-dual-architecture-proc...

The diagram is the last picture, and according to it you choose the ISA at the VM level: either Linux on s390x or Linux on arm64, but not both on the same VM.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#86

Post by ksec »

bmitc wrote: post #63
petcat wrote: post #9

Earlier quoted context omitted.

well that's nonsense. IBM does incredibly cool stuff. https://research.ibm.com/blog

What does IBM actually do? I just can never understand their business and operating model. It seems like they just do a bunch of random stuff and sell to the most enterprisey of enterprises.

>What does IBM actually do?

You should dive into the topic of Mainframe. There are a lot of financial transaction to other critical infrastructure are dependent on it. And not just because of backward compatibility but technical superiority.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#87

Post by userbinator »

The article is quite short on details but I wonder if this is an ARM core that can also execute IBM Z, or the other way around; in other words, which ISA does it execute its first instruction at the reset vector? In that past I've worked on a conceptual design for an "x86+" CPU, which would start as a regular x86 but then be able to execute code of other architectures like ARM, MIPS, PPC, etc. isolated in their own code segments, similar to how V86 mode works.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#88

Post by u1hcw9nx »

Not explained in the article:

Every single physical core on the chip decodes and executes both s390x and Arm AArch64 instructions, dynamically switching between the two ISA modes and convert them into micro ops. Mode switching is hypervisor-driven.

And those chips are fast. 5.7 Ghz 2nm node.

For who: When you need to run Linux programs on high security, mission critical environment. Others should not care.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#89

Post by __lm__ »

avhception wrote: post #43
rbanffy wrote: post #30

Earlier quoted context omitted.

ARM has better software support for AI applications and half of their presentation was about their inference accelerators that can go in the mainframes (and POWER machines). IBM mainframes are almost designed by their users. The previous generation skipped a lot of speed boost on the CPU side because their users didn’t want the machine to blow over their power delivery limits. Now, with their architecture behind it,…

At least back in the day, there was talk about Nvidia + ppc64le. Wasn't there even a supercomputer with that setup? But I guess that has fallen by the wayside.

We have some older Power9 with NVIDIA V100. Nvidia drivers stopped a while ago (before V100 were considered “old” also for x86_64).

The main problem is software support by most machine learning libraries. While it is normal to have to compile many things from source when the binary is not provided even by some third party, in some cases the software will not compile on ppc64le and surely is not tested to work.

Re: IBM Unveils Next Generation Dual-Architecture Processor for IBM Z and LinuxONE

#90

Post by bob1029 »

wmf wrote: post #75
bitwize wrote: post #69

Earlier quoted context omitted.

A single mainframe can handle workloads that would take dozens of x86 cloud servers, with nine nines of uptime. If you can afford it it pays for itself in terms of reliability and scalability.

That may be true but the dozens of x86 servers are cheaper and easier to use.

Sometimes quality of service matters more than cost.

If the consumer segment started to develop a sense that their payment cards were glitchy or unreliable, our economy could suffer real consequences. Error free, secure, instant payment experiences are essential. Go visit a local grocery store and measure how long it takes to authorize a transaction each time a card is presented to the terminal. Pay special attention to how fast the Visa and American Express networks are. At my local Kroger the terminal and network setup is so fast that you can use the chip reader almost like a mag stripe reader.

https://usa.visa.com/about-visa/newsroom/press-releases.rele...

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