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A third world engineer responds to “RISC-V: They should have known better”

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Re: A third world engineer responds to “RISC-V: They should have known better”

#341

Post by ben-schaaf »

LeFantome wrote: post #340
ben-schaaf wrote: post #266

Earlier quoted context omitted.

I've seen this claimed before, and just going by SiFive's specint claims the P870 at 2.6GHz should match Zen 3. But for SiFive's last silicon, the HiFive Premier P550, they claimed a specint2006 of 8.65/GHz. That should put the silicon only about 20% slower than an intel i5-6400. But if you look at geekbench scores it's about an order of magnitude slower. Correct me if I'm wrong, but Tenstorrent has yet to ship any o…

> I'd expect Raspberry Pi 4 levels of performance Well, there is some speculation regarding these chips so no sense arguing too much about it. That said, the SpacemiT K3 is already faster than a Pi 4 and even substantially faster than a Pi 5 for multi-core and vector stuff. And that is before counting the other 8 “AI cores” it has. These chips will be quite a bit faster than a K3, so certainly much faster than a Pi 4…

Neat! Hopefully these new architectures can beat the Pi5, though even that's still far away from Zen 1 let alone Zen 3.

> and even substantially faster than a Pi 5 for multi-core and vector stuff

I'll push back a little on this. It can be faster under certain workloads, but is not universally. It's behind in geekbench https://browser.geekbench.com/v7/cpu/compare/146501?baseline..., and in compilation workloads: https://www.phoronix.com/review/spacemit-k3-pico-itx/3

Re: A third world engineer responds to “RISC-V: They should have known better”

#342

Post by sylware »

zephen wrote: post #301
sylware wrote: post #290

Earlier quoted context omitted.

Allright, you did describe a monstruous IP mine-field. No way anybody could reasonably use anything else than RISC-V.

Bleeding edge processor development is always going to be a patent minefield, even for RISC-V. Most patents are broad enough to cover more than one architecture. But there are now several RISC-V IP vendors, and ARM can't possibly shut them all down, and companies can develop IP in-house, so there are lots of different designs already out there. So, at this point, developing a RISC-V processor provides a certain amoun…

Then RISC-V would need something like they did for open source software (in countries with barbaric IP), some sort of pool of defensive IP.

Because, if you look at the current trajectory of RISC-V micro-architectures: they will be competitive, so current hardware big tech will try hard to shut them down. If they are already at Zen3 performance... I run Zen2 and it's already beyond than enough (I miss AVX512 extensions though, hope we'll get often RVA cache line vector instructions on RISC-V).

Look at qualcomm already buying what seems to be a very good RISC-V microarchitecture, wonder what they will do to it (usually, they let it die slowly forcing their good engineers to work on something else).

The right way(TM) would be for ARM to "drop its ISA" and become a microarchitecture designer able to decode and run RISC-V ISA.

Intel and AMD should too. The world would be basically competing micro-archs all with high compatibility at machine code level.

And it seems nobody has been addressing the elephant in the room: x86 is an horrible ISA for a modern CPU, much more worse than RISC-V/ARM. It is only because AMD/Intel throw tons of money with tons of brains to make that horrible ISA performant AND because they are hogging the production capacity of the best silicon process.

There is zero wonders here.

Re: A third world engineer responds to “RISC-V: They should have known better”

#343

Post by zephen »

sylware wrote: post #342
zephen wrote: post #301

Earlier quoted context omitted.

Bleeding edge processor development is always going to be a patent minefield, even for RISC-V. Most patents are broad enough to cover more than one architecture. But there are now several RISC-V IP vendors, and ARM can't possibly shut them all down, and companies can develop IP in-house, so there are lots of different designs already out there. So, at this point, developing a RISC-V processor provides a certain amoun…

Then RISC-V would need something like they did for open source software (in countries with barbaric IP), some sort of pool of defensive IP. Because, if you look at the current trajectory of RISC-V micro-architectures: they will be competitive, so current hardware big tech will try hard to shut them down. If they are already at Zen3 performance... I run Zen2 and it's already beyond than enough (I miss AVX512 extension…

There are two different categories of patent issues at play here, and several different implications for competition.

The first issue is on the purely physical level. The fabs (and integrated companies like Intel) fight this one out, and eye each others' patent stacks and maybe exchange a bit of money. This is not something the average Joe can worry about; nobody has the money to build the fab or engage in the chemical and materials research.

The second issue and implication is on the logic and circuitry level. The average Joe is not going to be able to design and test something really big and performant, but many companies (not just Intel, AMD, and ARM) are capable of this, and again, money might change hands, but (aside from things like China) absolute shutting down of competitors is not really going to happen.

So big players will dominate the highest performance market, but at least there are probably a dozen or so of them, so that will provide some pressure on its own.

Lower performance chips (some of which will be more than performant enough for many niches) will probably proliferate. The profit margin on these chips will be cutthroat, because the average Joe can design them, and then needs to negotiate with, e.g. TSMC, to actually build the damn things.

And a lot of innovation will happen in these lower-level chips as well. Expect many startups to be bought by the bigger players to enhance their own patent portfolios. And expect that their competitive prices will also drive down the cost of the most performant chips a bit.

The performance chip companies will have interesting choices to make. Lower the price to knock out the competition below? Or raise the price? If they raise the price too much, their available market will shrink, and then they'll need to raise the price even more.

Re: A third world engineer responds to “RISC-V: They should have known better”

#344

Post by sylware »

zephen wrote: post #343
sylware wrote: post #342

Earlier quoted context omitted.

Then RISC-V would need something like they did for open source software (in countries with barbaric IP), some sort of pool of defensive IP. Because, if you look at the current trajectory of RISC-V micro-architectures: they will be competitive, so current hardware big tech will try hard to shut them down. If they are already at Zen3 performance... I run Zen2 and it's already beyond than enough (I miss AVX512 extension…

There are two different categories of patent issues at play here, and several different implications for competition. The first issue is on the purely physical level. The fabs (and integrated companies like Intel) fight this one out, and eye each others' patent stacks and maybe exchange a bit of money. This is not something the average Joe can worry about; nobody has the money to build the fab or engage in the chemic…

Indeed, if NVIDIA or SAMSUNG go super performant RISC-V implementations, things are very probably going to change.

Re: A third world engineer responds to “RISC-V: They should have known better”

#345

Post by peterfirefly »

anon-3988 wrote: post #214
strenholme wrote: post #201

Earlier quoted context omitted.

Getting RISC-V to have better performance is a matter of in-chip optimizations (caches, pipelines, etc.) and high quality performance oriented fabs. The dominance of x86 after the dot-com bubble popped shows that one can get incredible performance even from an ISA which is a hack on top of a hack on top of another hack. [1] In terms of a “theoretically even better ISA”, if anyone has any proposals, I would love to se…

> [1] I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers, but 16 registers at least is quite a bit better than the 4-8 registers the 386 had. Is "registers" still a real thing or its just an illusion at this point? I am pretty sure there are "virtual" registers or micro instructions (something like that, I forgot the terminology)

They are real on slow CPUs and an illusion on medium to fast CPUs where they are just "value names" (register renaming, physical vs virtual registers).

You can still run out of value names, though. We rarely run out of them in straight-line code, we sometimes run out in absurd loop code, and we almost always have to do something for our function calls/returns to avoid running out -- we can't just assign each function its own set of value names. This means we need spill/restore instructions, either before and after the call instruction or at the beginning and end of the function. Sometimes both. We also divide our value names into parts that have to be saved by the caller and parts that have to be saved by the callee.

Maybe smarter call/return instructions will help a bit in the future by doing multiple register renames as part of a single instruction in order to make those spills/reloads faster/less necessary/more asynchronous.

Sparc and Itanic tried to do something like that (register stacks), but in a way that ended up being expensive to implement in hardware (high clock speeds were hard) and inflexible in practice -- and also annoying to support for the OS, the compiler, and the debugger.

Re: A third world engineer responds to “RISC-V: They should have known better”

#346

Post by peterfirefly »

anon-3988 wrote: post #335
RetroTechie wrote: post #332

Earlier quoted context omitted.

> Is "registers" still a real thing or its just an illusion at this point? I am pretty sure there are "virtual" registers or micro instructions (something like that, I forgot the terminology) https://en.wikipedia.org/wiki/Register_renaming ? But yes, register count is still a thing. Why? If you run out of registers, operations 'spill out' into main memory. Read: L1 (data) cache. Which is fast, but not as fast as CPU…

> But yes, register count is still a thing. Why? If you run out of registers, operations 'spill out' into main memory. Read: L1 (data) cache. Which is fast, but not as fast as CPU registers. And probably uses a lot more transistors & power. Yes, register renaming. What I mean is that why does anyone care still what instruction I am running on? The CPU have its own microops, instruction decoder, its own pipeline, sche…

1024 is stretching it a bit but several hundred are normal for high-end CPUs -- while pretending to have 32 (+ usually 32 SIMD registers that may or may not overlap with the normal 32).

"[...] and pretend that it only have [sic] 32" is EXACTLY what register renaming is.

Re: A third world engineer responds to “RISC-V: They should have known better”

#347

Post by h3lp »

rasz wrote: post #220
kreelman wrote: post #215

Earlier quoted context omitted.

Here's the CH32v003, https://github.com/openwch/ch32v003 These are pretty low end and are fairly available at low cost. Here's a youtube of someone talking through some of the the CH32 boards, https://www.youtube.com/watch?v=Kss6WQvJbRs He talks about them being the "10c/chip" chip. Then, there is the CH32v303 https://www.wch-ic.com/products/CH32V303.html , which is the lower end of the chips that support minimal flo…

CH32v303 costs more than much more capable ARM based RP2354A

RPi is not less expensive; current Qty 1 lcsc price for rp2354b is $1.62, whereas ch32v303 is $0.88

Re: A third world engineer responds to “RISC-V: They should have known better”

#348

Post by porridgeraisin »

alephnerd wrote: post #313
porridgeraisin wrote: post #311

Earlier quoted context omitted.

I dont know about the social aspects since I don't live there, but as far as AI goes, it's not just HN. There is no place where you get balanced takes that match the work that we actually do day to day. I suspect part of this is accelerated by the media practices of the hyperscalers like anthropic and openai - they make doomerism super profitable for publishers. One of the most natural emergent counterweights to doom…

> I also feel it's topic-based. On general systems engineering, think databases, OS, architecture, webtech, the SNR on this site is generally amazing. But these days those articles are fewer than before. For example, 2 years back when every other article was about sqlite and postgres, while it was a very unidimensional few months, you could learn a lot from here I agree. The thing is, a lot of us moved to Lobsters [0…

Interesting, mind extending an invite? I completely forgot about that place. I remember it being the one that blocked the brave browser. Doesn't seem to be the case anymore though.

Re: A third world engineer responds to “RISC-V: They should have known better”

#349

Post by letmehelpyou »

genxy wrote: post #252
TMWNN wrote: post #251

Earlier quoted context omitted.

I didn't get that impression. He talks about T&T (and places like that)'s inability to cheaply obtain components, but that's not the main point of his post

Parent wanted to drop some anti-woke whistles because the author is black. Engineer from T&T makes a sound economic argument for the RISC-V ecosystem and suddenly it is "social justice". F that.

[dead]

Re: A third world engineer responds to “RISC-V: They should have known better”

#350

Post by Conan_Kudo »

initramfs wrote: post #306
Conan_Kudo wrote: post #296

Earlier quoted context omitted.

OpenSPARC is under the GPL, which is probably why it didn't go anywhere directly . OpenPOWER is under permissive creative commons licenses, and people are iterating on the open source cores released by them. But the arrangement with efabless didn't go anywhere, and the company shut down last year without warning. So there's nowhere to experiment with producing chips.

https://wafer.space allows chips but I think tinytapeout became what efabless was doing: https://chipfoundry.io/ Also Hitachi's SH-2 & SH-4 patents expired in 2016, so J-core picked up where they left off: https://j-core.org/ MIPS also went open source around 2018: https://www.datacenterknowledge.com/data-center-hardware/mip...

The "MIPS Open" program never launched. MIPS itself eventually pivoted to RISC-V, and is now owned by Globalfoundries.

I don't think the j-core effort is still active? It would be interesting to see it continue, though.

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