> ARM was also rooted in an academic exercise. Where do people get ideas like this from? Just nonsense.
ARM, the ISA, is wholly rooted in academic exercises like Berkeley RISC. What do you think happened? RISC-I and RISC-II never existed, ARM means "Automated Reasoning Mechanism" and the ISA was never RISC whatsoever? Talk about nonsense, damn...
No, ARM means "Acorn RISC Machine" and was developed by Acorn Computers, a British computer manufacturer, because the 8-bit MOS 6502 they had based their previous designs on was obsolete, available 16-bit processors "a bit crap"[0] and available 32-bit designs too expensive. So the ARM ISA was developed by a computer manufacturer for use in their own chips in their own products, quite far from an "academic exercise".
> The only argument I've ever seen for RISC-V that's vaguely logical is that there's no licensing to Arm involved, but since I can get M0/M3 devices for a dollar or so with infinite tool and library support that's something that's totally irrelevant for most users. How expensive is it to license the instruction set so you can expand it?
Dunno, I'm still saving up for the billion-dollar fab I'll need before I can think about licensing an instruction set. As an aside, Espressif (or Xtensa if you want to split hairs) have been quietly doing a lot of what RISC-V is supposed to do for years now. I know they've also been fiddling with RV32's but all the real work is LX6/LX7. They're best-known for their use in ESP32s but they also crop up in an awful lot…
My point is that if an ARM chip costs 1$ then how much is licensing? 0.1$? 0.5$? That’s money that doesn’t need to go to ARM if everyone is using unlicensed instruction sets.
> The only argument I've ever seen for RISC-V that's vaguely logical is that there's no licensing to Arm involved, but since I can get M0/M3 devices for a dollar or so with infinite tool and library support that's something that's totally irrelevant for most users. How expensive is it to license the instruction set so you can expand it?
Surely those expanding the instruction set do not fall into "most users"?
Everyone is paying for the license. Expanding was poorly phrased but the per-unit licensing cost might not be irrelevant. It might even make smaller batches cost-efficient for smaller manufacturers if they use an instruction set that doesn’t require a license.
If every one has a hammer and a saw and identical wood planks, everyone can build a frame that holds up 100 years? Think it through. This is the HN comment section after all.
Yes. That's the point of AI. Anyone can make anything just as easily and well as anyone else.
That’s just not how things work. Some one with experience and knowledge will be measurably more productive and build a better whatever no matter how much spicy autocomplete they have at their disposal.
Even if you eventually figure out all the right questions to prompt, the experienced person is long done
MIPS or PowerPC is also free. We can use them too.
Not free enough. If your stuff becomes popular, you'll see patent holders popping and ask for money.
The PowerPC G5 was released in 2003. Patents last 20 years, so they expired 3 years ago. If a G5 isn't powerful enough for your use case, I don't know what is.
The RISC-V fusion arguments from back in ~2018 didn't really pan out. A lot of those fusion opportunities are just instructions now. slli + add? Zba (sh*add). slli + srli? Zbb (zext.*). slli + srai? Believe it or not, also Zbb (sext.*). Look at that pair of RVC instructions you used instead of a single 32-bit opcode. They are: * Taking up valuable compressed instruction space; each compressed codepoint has an opportu…
Sorry, haven't been following along, but sounds to me that the argument was a valid one seeing how it made the designers add new instructions. Not sure if there's an impact caused by the late addition as opposed to always having them, but considering this is a fairly core thing what a program does, not sure what degree of fragmentation this causes on the level of compilers and hardware. x86 effectively killed innovat…
Not seeing this at all. We routinely and easily target SSE4, AVX2, AVX-512 (in four variants) using the same application code in one binary.
Frankly, this seems better to me than four separate RISC-V matmul extensions.