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A third world engineer responds to “RISC-V: They should have known better”

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Re: A third world engineer responds to “RISC-V: They should have known better”

#241

Post by camel-cdr »

orangeboats wrote: post #177
camel-cdr wrote: post #108

Earlier quoted context omitted.

Here are a few random things I know of: * Tenstorrent Ascalon has a neat optimization for certain LMUL>1 SIMD operations. LMUL=2 effectively unrolls the SIMD operation making it read two SIMD registers from every source and write two SIMD registers to the destination. There are however some instructions where LMUL=2 only needs to write to one registers, those are narrowing instructions (e.g. 64-bit to 32-bit truncati…

>While the scalar part of OpenXiangShan looks really good, the RVV imolementation is currently basically unusable. Good news! It seems they just opened a new PR for a new RVV implementation: https://github.com/OpenXiangShan/XiangShan/pull/6331

Great news! How did I miss that?

I'll have to try out the branch.

Re: A third world engineer responds to “RISC-V: They should have known better”

#242

Post by nicman23 »

phire wrote: post #152
andai wrote: post #146

Earlier quoted context omitted.

Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance. I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanentl…

No. Intel and AMD have proven that if you throw enough money at the problem, you can make fast microarchitectures despite a flawed ISA, and in many ways RISC-V is less flawed than x86. The things we are debating here are more along the lines of minor nitpicks. The main roadblock to the existence of fast RISC-V cores is the entrenchment of large x86 and arm ecosystems.

the x86 is just an abstraction layer at this point

Re: A third world engineer responds to “RISC-V: They should have known better”

#244

Post by camel-cdr »

LeFantome wrote: post #197
acutelittlebox wrote: post #153

Earlier quoted context omitted.

the current highest performance RISC-V systems you can buy off a shelf are equivalent to a raspberry pi 5 so they're not terribly behind. in terms of IPC, currently available RISC-V cores are already basically on par with Zen 3 and Apple M1 from what i understand and Jim Keller believes that RISC-V will be the one that leads the way for raw performance.

SiFive P870 and Tenstorrent Ascalon are pretty much Zen 3. Tenstorrent is supposed to be releasing silicon soon. You can license their cores now. SiFive says customers have the P870 already but I am not sure who those are.

I think it will be closer to Zen 1/2

Re: A third world engineer responds to “RISC-V: They should have known better”

#245

Post by mrheosuper »

acutelittlebox wrote: post #236
mrheosuper wrote: post #232

Earlier quoted context omitted.

And then OP rants about cost of debugger > A debugger for an ARM part alone a Segger J-Link costs about $600, though I guess for that $100, and add another $100 to ship,so about $200 I could get an EDU edition J-link and no chips or boards. Yaay. This is bad comparison, you can debug arm soc with <10$ debugger too/

i think the part that you're missing is that this is what it's like for him and people in similar regions where a huge amount of things aren't an option to begin with and many more things are far more expensive than in the US or Europe. a lot of the article is about how the best part about RISC-V is that the chips and tools are available to more of the world.

I also live in 3rd country, and i know the pain.

But if you can access to RISC V IC/tools, you can access ARM IC/tools. The Chinese basically spams those ARM IC as many(if not more) as RISC V IC.

To me the author tried to hate ARM for no reason.

Re: A third world engineer responds to “RISC-V: They should have known better”

#246

Post by imtringued »

andai wrote: post #146
ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance. I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanentl…

So far the vast majority of complaints have been nothing burgers.

The biggest valid complaint is the lack of dedicated mask registers for vector processing, that's a huge design flaw in the vector instructions since it makes register renaming and shadow registers mandatory. In other words, the problem here is that they didn't stick with the RISC philosophy of making everything explicit.

Compressed instructions are mostly wasted encoding space, but from a performance perspective they don't matter. If they are slow then compilers will treat them as slow legacy instructions and stop using them or they will only emit aligned compressed instructions.

Re: A third world engineer responds to “RISC-V: They should have known better”

#247

Post by ant6n »

dmitrygr wrote: post #192
andai wrote: post #146

Earlier quoted context omitted.

Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance. I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanentl…

With enough effort, you can make a brick fly. X86 proves this. But if you are designing a new flying device, despite the fact that you could make a brick fly, you probably don’t want to design a brick. Why make it harder on yourself? Riscv took all this information in, and designed a very, very good brick.

Wait, so RiscV is still also a brick, like x86?

Re: A third world engineer responds to “RISC-V: They should have known better”

#248

Post by HexDecOctBin »

rurban wrote: post #237
jiqiren wrote: post #119

Earlier quoted context omitted.

He's saying that shipping from the big western parts suppliers (Digikey, Mouser, Segger) costs a lot of money. When ordering from AliExpress or Crowd Supply he just gets the cheap postal rates which from China are free. It is very likely a good chunk of the overhead from western part suppliers has to do with export controls and risk aversion. Aliexpress doesn't do any ID verification hassle. This is all an argument m…

It's not just Western shipping parts. You can buy cheap Indian parts, and have the very, same insane shipping costs as with "Western" parts. Ie a 2€ part from India will still cost 25€, whilst the 2€ part from China will cost 2-4€

Why is that? Is it simply a matter of scale (not enough shipping containers leaving from India to Trinidad and Tobago)?

Re: A third world engineer responds to “RISC-V: They should have known better”

#249

Post by nottorp »

handwarmers wrote: post #25
alephnerd wrote: post #5

Earlier quoted context omitted.

> it's a breath of fresh air compared to the usual bay area centric takes... HN hasn't been Bay Area centric in years. Honestly, most comments and usership on the platform seems to now align with SWE culture in DACH and CEE. Presumed RISC-V hate is a perfect example of that - the UCs and CSUs have been using RISC-V in their curriculum since the 2010s becuase Patterson is faculty at Cal and most CompArch courses in bo…

the fact that this comment is getting downvoted into oblivion instead of discussed is poignant enough. fwiw, my experience is similar. hn has not been about startups, vc funding, or anything in that space for quite a while. to paraphrase a classic, this place is like a memory of the forum we used to love, and the memory is fading.

The "AI" spam is significantly more prevalent than the blockchain spam used to be, but HN has always had its spam waves.

Blockchain is all but dead, even the "i've rewritten this thing, it has far less features but it's IN RUST" spam has greatly reduced.

Re: A third world engineer responds to “RISC-V: They should have known better”

#250

Post by genxy »

LeFantome wrote: post #224
muyuu wrote: post #160

Earlier quoted context omitted.

the main problem with RISC-V is also the main selling point: there is no single owner company behind steering development and making sweeping decisions how will that pan out over the long term is really unclear and the reality is performance is actually catching up quickly

History tells us that open standards pretty much always beat out proprietary ones in the end. You cannot buy the company backing RISC-V to take out the competition. And if a RISC-V company stumbles, the ecosystem carries on. But if even one RISC-V company is in the right place at the right time, RISC-V can surge ahead. It is hard to imagine it does not dominate eventually.

Which is really the subtext to Grinberg's rant. It has technical flaws that he dislikes, but those won't stop RISC-V from dominating in the market.

You get these kinds of responses when something is too close to perfection. It suddenly gets judged in a much different light.

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