Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

SIMD in the 90s: Programming Intel's Pentium MMX

pikuma.com

Post reply on HN
Print view View original

41–50 of 74 posts

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#41

Post by ColdStream »

ack_complete wrote: post #32
jamesu wrote: post #31

Earlier quoted context omitted.

AFAIK, MMX was more for fixed point math (as also pointed out by another commenter) which would explain why it wasn't used much for 3D. You tended to see it more in image and sound processing code. Maybe the reviewers got it mixed up with 3DNow.

MMX did help significantly with software 3D rendering. I worked on a software rasterizer that benefited significantly from it. But it didn't take long before even a well-optimized software renderer on a high end CPU couldn't keep up with a low end GPU on a low end CPU.

[dead]

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#42

Post by wormius »

Nition wrote: post #14
theandrewbailey wrote: post #9

> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.

I remember hearing a rumour as a young teen that the Coppermine codename meant it actually had copper wiring and that's what made it faster somehow. Copper has lower resistance than aluminium and can therefore help chips run faster - it makes sense! But it was just a codename and the coppermine had aluminium interconnects. My family got a PIII 533Mhz coppermine, in the early sideways Slot 1 configuration. Blazing fas…

C-f "pod"

There it is :)

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#44

Post by Panzerschrek »

John Carmack promised that Quake II will use MMX, but this wasn't done. That's why software rendering in Quake II is so boring, it doesn't even support colored lighting. In the other hand Unreal did use MMX, which allowed it to work in 32-bit color mode with colored lighting and a bunch of other effects.

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#46

Post by krige »

Panzerschrek wrote: post #44

John Carmack promised that Quake II will use MMX, but this wasn't done. That's why software rendering in Quake II is so boring, it doesn't even support colored lighting. In the other hand Unreal did use MMX, which allowed it to work in 32-bit color mode with colored lighting and a bunch of other effects.

IME Q2 also ran much slower on comparable hardware despite looking worse. The first rig I played them on was an unaccelerated P200MX with a paltry 32 megs of RAM and Q2 struggled at 320x240 while Unreal was slightly choppy but acceptable at 400x300.

Good lord, 400x300.

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#47

Post by Agingcoder »

theandrewbailey wrote: post #9

> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.

I got bitten by that one - I remember my 3d engine going all wrong because I hadn’t realized I couldn’t mix mmx and fpu registers unless I was willing to pay for the extraordinarily expensive EMMS (?) instruction

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#48

Post by kstenerud »

I still remember the MMX TV campaign they put out in the 90s.

https://www.youtube.com/watch?v=5zyjSBSvqPc

https://www.youtube.com/watch?v=cnEuWfFTuxg

I was watching this and thinking "Who's going to even understand what this is about? Why is this playing on primetime TV?" Playing video on a computer wasn't a thing at the family consumer level at this time, and gaming was still a geeky niche.

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#49

Post by Nition »

245425456g wrote: post #40
Nition wrote: post #14

Earlier quoted context omitted.

I remember hearing a rumour as a young teen that the Coppermine codename meant it actually had copper wiring and that's what made it faster somehow. Copper has lower resistance than aluminium and can therefore help chips run faster - it makes sense! But it was just a codename and the coppermine had aluminium interconnects. My family got a PIII 533Mhz coppermine, in the early sideways Slot 1 configuration. Blazing fas…

P3 Coppermine was 0.18 µm. P3 Tualatin was 0.13 µm with Cu and low-K. So no, Coppermine had nothing to do with Cu in the process.

Wow, I never knew they actually did switch to copper on the next model. What a missed naming opportunity.

Re: SIMD in the 90s: Programming Intel's Pentium MMX

#50

Post by spider-mario »

grg0 wrote: post #3
Const-me wrote: post #2

I would add than SSE1 and SSE2 are now required parts of AMD64 instruction set. All 64-bit PC processors are required to support them both. For that reason, modern compilers are ignoring x87 FPU when building 64-bit binaries. Instead, they compile all float and double arithmetic into SSE1 and SSE2 instructions, respectively.

Which is not to say that they are necessarily auto-vectorizing. You know wassup when you see vaddsd instead of vaddpd. And ideally you'd use AVX-512 to saturate a modern cache line if you can afford to drop support for the older devices.

Or runtime CPU detection and dispatch to support both.
Post reply on HN