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A third world engineer responds to “RISC-V: They should have known better”

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Re: A third world engineer responds to “RISC-V: They should have known better”

#231

Post by Johanx64 »

ghostly_s wrote: post #141

I lost the thread of his argument when he brought up the shipping expense: > I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on then follows with: > the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings. When shipping is so exp…

Difference between $1 and $.10 is always irrelevant unless you're mass manufacturing, which I presume you aren't on a remote island.

Plus, arm cortex-m0+ cores aren't $1, they are also available in $.15-$.30 range.

Westeners like to buy the $.10 CH32V003 as an exercise in minimalism, after all its refreshing to work in an environment with very limited resources. For the same reason people enjoy 1KB demoscene categories.

There's no economics behind it.

Authors argument almost entirely leans on Aliexpress shipping things for "free" to his island. It also has arm cores, but I suppose RISC-V MCUs have smaller odds of being fakes/clones.

Re: A third world engineer responds to “RISC-V: They should have known better”

#232

Post by mrheosuper »

mrheosuper wrote: post #228

> From that position, the difference between a ten cent part and a one dollar part is not a rounding error Idk, if your shipping cost is $120, it sounds to me $1 is rounding error.

And then OP rants about cost of debugger

> A debugger for an ARM part alone a Segger J-Link costs about $600, though I guess for that $100, and add another $100 to ship,so about $200 I could get an EDU edition J-link and no chips or boards. Yaay.

This is bad comparison, you can debug arm soc with <10$ debugger too/

Re: A third world engineer responds to “RISC-V: They should have known better”

#233

Post by hakfoo »

rasz wrote: post #220
kreelman wrote: post #215

Earlier quoted context omitted.

Here's the CH32v003, https://github.com/openwch/ch32v003 These are pretty low end and are fairly available at low cost. Here's a youtube of someone talking through some of the the CH32 boards, https://www.youtube.com/watch?v=Kss6WQvJbRs He talks about them being the "10c/chip" chip. Then, there is the CH32v303 https://www.wch-ic.com/products/CH32V303.html , which is the lower end of the chips that support minimal flo…

CH32v303 costs more than much more capable ARM based RP2354A

I feel like the Raspberry Pi products are inherently a special case.

They're probably produced in far greater numbers than most off-the-shelf STM32 or CH32V chips. You've got a huge ready market in hobbyist/educational products as well as the commercial products that have used it as a convenient choice.

There's that whole non-profit/educational heritage around them that likely selects for a different set of defaults and features than, say, a MCU designed specifically to be the controller for a SATA SSD or a $19 Roku clone.

They also have a small product range, as compared to the broad product matrix a lot of the more "commercial brand" MCUs come in. I know even the CH32v30x chips come in several variations multiplied by several package options (which vary enough to impact the features you can realistically use on them).

Re: A third world engineer responds to “RISC-V: They should have known better”

#234

Post by MrBuddyCasino »

ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

> I think he's kind of speaking past the original author.

Thats being generous. He is spinning this into a 3rd world / 1st world social justice story, while ignoring the technical points dmitry made.

Re: A third world engineer responds to “RISC-V: They should have known better”

#236

Post by acutelittlebox »

mrheosuper wrote: post #232
mrheosuper wrote: post #228

> From that position, the difference between a ten cent part and a one dollar part is not a rounding error Idk, if your shipping cost is $120, it sounds to me $1 is rounding error.

And then OP rants about cost of debugger > A debugger for an ARM part alone a Segger J-Link costs about $600, though I guess for that $100, and add another $100 to ship,so about $200 I could get an EDU edition J-link and no chips or boards. Yaay. This is bad comparison, you can debug arm soc with <10$ debugger too/

i think the part that you're missing is that this is what it's like for him and people in similar regions where a huge amount of things aren't an option to begin with and many more things are far more expensive than in the US or Europe. a lot of the article is about how the best part about RISC-V is that the chips and tools are available to more of the world.

Re: A third world engineer responds to “RISC-V: They should have known better”

#237

Post by rurban »

jiqiren wrote: post #119
kelnos wrote: post #102

I don't really understand the author's conclusions about cost and shipping, and how RISC-V is cheaper and more accessible to people outside the US and Europe. He first talks about how getting $1 worth of chips can cost $60-$200 in shipping for him due to his location... but then by the end claims that RISC-V gives him "an architecture that arrives in my country at ten cents a part". I don't get how both things can be…

He's saying that shipping from the big western parts suppliers (Digikey, Mouser, Segger) costs a lot of money. When ordering from AliExpress or Crowd Supply he just gets the cheap postal rates which from China are free. It is very likely a good chunk of the overhead from western part suppliers has to do with export controls and risk aversion. Aliexpress doesn't do any ID verification hassle. This is all an argument m…

It's not just Western shipping parts. You can buy cheap Indian parts, and have the very, same insane shipping costs as with "Western" parts. Ie a 2€ part from India will still cost 25€, whilst the 2€ part from China will cost 2-4€

Re: A third world engineer responds to “RISC-V: They should have known better”

#238

Post by inkyoto »

strenholme wrote: post #187

I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64. This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86…

Competing RISC designs tanked for a number of reasons, but not just because Intel and AMD started pumping money into their products.

RISC vendors were in the business of selling hi-end workstations and servers that required their own respective RISC CPU's, which meant that each vendor had its own, in-house CPU design arm and either their own fab or they outsourced the CPU manufacturing to someone else. In a way, the RISC CPU was a by-product of what they sold but never the product they sold alone. Two problems followed.

The CPU design is an expensive process, and keeping one's own fabs up to date with the latest and greatest manufacturing process is even more expensive, especially as the designs and processes advanced. It eventually became prohibitively expensive to maintain one's own fab, and RISC vendors started falling behind the bleeding edge (DEC, Motorola, etc.). IBM managed to get away with it for a time, but eventually, they also divested.

The second problem concerned the outsourcing of the CPU manufacturing. Those RISC vendors (e.g. SGI with their MIPS) who did not have their own fabs had to contract a fab (e.g. NEC). Such a fab would produce a diverse range of microchip products, and a CPU would be just one of them. Which typically meant not the latest and greatest process, but at least a generation behind.

Whereas both Intel and AMD were dedicated CPU design and manufacturing houses (although AMD also divested their fabs later), so they could specifically focus on what mattered for CPU's and for CPU's only.

That said, for Intel and AMD, the CPU was the product, whereas for the RISC vendors, it was not, however important, the CPU was for them.

Re: A third world engineer responds to “RISC-V: They should have known better”

#239

Post by inkyoto »

anon-3988 wrote: post #214
strenholme wrote: post #201

Earlier quoted context omitted.

Getting RISC-V to have better performance is a matter of in-chip optimizations (caches, pipelines, etc.) and high quality performance oriented fabs. The dominance of x86 after the dot-com bubble popped shows that one can get incredible performance even from an ISA which is a hack on top of a hack on top of another hack. [1] In terms of a “theoretically even better ISA”, if anyone has any proposals, I would love to se…

> [1] I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers, but 16 registers at least is quite a bit better than the 4-8 registers the 386 had. Is "registers" still a real thing or its just an illusion at this point? I am pretty sure there are "virtual" registers or micro instructions (something like that, I forgot the terminology)

Registers are very much real, and their number being available at the ISA level will continue to matter regardless of the actual number of shadow registers.

Being able to store, e.g. 10 vs 5, local variables in a larger register file has performance implications[0] strong enough to consider larger register files an advantage.

[0] The reduced number of memory-to-CPU and vice versa data transfers for transient computation results.

Re: A third world engineer responds to “RISC-V: They should have known better”

#240

Post by Karrot_Kream »

snowpid wrote: post #225
alephnerd wrote: post #218

Earlier quoted context omitted.

> How would you say the "IRL conversation topics in the Bay Area tech scene" diverge from HN For starters, most Bay Area residents are not active on HN on a sunny Sunday afternoon during peak brunch time, a Giants v Rockies game, a social race in the Marina, during the weekend right before college move-in begins for a number of UCs, and the first weekend after the K-12 school year started. Secondly, the technical con…

Pickleball and Hyrox is very common in the DACH region, Hyrox was invented in Hamburg... " Furthermore, the Ivy-versus-nonIvy division and rhetoric is nonexistent in the Bay. " Non existent in DACH region or CEE because why should it? " Thirdly, the vibe change around layoffs the job market is completely different. While there have been plenty of layoffs (and friends and acquaintances of mine have been impacted), mos…

No I'm a long time Bay Area tech person also and what alephnerd is saying tracks with the interest profile of my circle as well. Predictably I was not on HN during a great weather day with plenty going on. This weekend was also Oakland Pride :)

I haven't done the analysis to see whether it's DACH influenced or not but the rhetoric here does not feel Bay Area shaped at all and hasn't for years. It feels like what happens when too many people read about the Valley from too many Techcrunch articles but don't actually live here. It's largely a worldview composed of too many online articles and gripes.

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