Sahil
Assembly Hall of Shame
71–80 of 110 posts
Re: Assembly Hall of Shame
#72This author also has other things like: A compiler that emits only `mov` instructions and another compiler that deliberately messes with the control flow so that, if disassembled, common debuggers will draw symbols like skulls or threats. https://github.com/xoreaxeaxeax/repsych
He also bruteforced the entire opcode space to find undocumented instructions (sandsifter).
Also came up with the original ..cantor.dust.. binary visualization tool, which is a tool I never used directly but Chris' presentation of it in 2012 is still one of the coolest talks I've ever seen.
Re: Assembly Hall of Shame
#73Earlier quoted context omitted.
No, that's done by the decoder. It actually does nothing.
The decoder is an implementation detail that is a subcomponent of NOP; GP was right, and your correction isn't.
As specified by the spec, it arguably increments RIP by one.
The actual typical hardware implementation just fetches the next 16-32 bytes from icache, shifts it to the correct alignment, and slams it into a bunch of parallel decoders which each attempts to decode one x86 instruction per byte.
The next cycle, the first 1-6 non-overlapping valid instructions are accepted into a queue for further decoding. The NOP almost certainly takes up space in this queue.
At no point does RIP get incremented by one. There isn't even a single physical RIP register to increment, the CPU is "executing" dozens or even hundreds of RIPs in parallel.
Re: Assembly Hall of Shame
#74Bus cycles can be arbitrarily long on any processor that has memory cycles with a hand shake requiring an ack, with no timeout. E.g. we can build a board around a MC68000 where we make it lock up forever in a bus cycle, waiting for a DTACK that doesn't arrive. Some early microprocessors had clocked bus cycles without handshaking. They would put out an address on some address lines and signal some line together with a…
In general, more complex processors have latency issues, and in some ways modern chips have actually become worse with each design iteration.
https://en.wikipedia.org/wiki/Metastability_(electronics)
Ultimately... failure modes must arise because naive gate design simulation models can't determine issues in a computationally feasible time frame.
The consequences of "fixing" CDC prone design flaws makes a processor many times slower (8 to 16 times slower on my dumb attempt), and develops weird alien design features very different from Von Neumann architectures.
This is why we can't have nice things. =3
Re: Assembly Hall of Shame
#75I wonder if you can do some damage with scatter/gather ops within a VM, such that each fetch is a TLB miss inside the VM, and every table walk fetch is a TLB miss outside of the VM (which gets you up to 24 "fetches per fetch").
Re: Assembly Hall of Shame
#76PCIe is more like a packet-switched network than a bus, which is incidentally why things like Thunderbolt (effectively external PCIe) and sillier demonstrations like https://www.youtube.com/watch?v=q5xvwPa3r7M work.
...and with things like https://en.wikipedia.org/wiki/ExpEther , you can get even higher latencies.
Re: Assembly Hall of Shame
#77Earlier quoted context omitted.
ADD does in fact do that.
I'm not disputing the total effect. I'm asking if you'd rather describe ADD and JMP in this manner, in order to say that NOP does not in fact do nothing.
Love the pedantry here. I'm currently at: no op code does anything, it's all fancy effects in the hardware that can be described in arbitrary detail, which somehow allows me to cause these letters to appear on your screen.
Re: Assembly Hall of Shame
#78Earlier quoted context omitted.
I thought I remembered reading somewhere re: the 8086 microcode disassembly that NOP, which is encoded as XCHG AX,AX actually does run the XCHG microcode and uses an internal scratchpad register to do the exchange.
There were several NOPs - XCHG BX,BX and so on. Those were taken later to be prefixes for new classes of opcodes.
None was. XCHG AX,AX is special because XCHG AX,reg has a one-byte encoding.
You're probably confusing with:
- POP CS being broken and later becoming a prefix
- some opcodes being "reserved NOPs", i.e. reserved without generating #UD. They are used for instructions that may be defined in the future while guaranteeing backwards compatibility, for example new kinds of prefetches. MPX bounds checking instructions were also encoded in reserved NOPs.
Re: Assembly Hall of Shame
#79Earlier quoted context omitted.
I wish they would just explain it in normal terms instead of this nasty LLM "engaging blog post" style
I looked at both links and don't see anything weird or annoying, and I hate overblown styles myself.
‘The counters tell the story’ might be something they consider odd. But I’m not familiar with the author’s style so they could have had these tics pre-LLM or they picked up these tics from reading a lot of LLM content.
Re: Assembly Hall of Shame
#80Bus cycles can be arbitrarily long on any processor that has memory cycles with a hand shake requiring an ack, with no timeout. E.g. we can build a board around a MC68000 where we make it lock up forever in a bus cycle, waiting for a DTACK that doesn't arrive. Some early microprocessors had clocked bus cycles without handshaking. They would put out an address on some address lines and signal some line together with a…
Bus cycles can also be arbitrarily long on those microprocessors if they don't use dynamic logic - you can stop the clock.