Earlier quoted context omitted.
It increments rip by one.
No, that's done by the decoder. It actually does nothing.
It's still part of the instruction to increment it by one, as opposed to write a value or offset to it, as jump instructions do.
Assembly Hall of Shame
61–70 of 110 posts
Re: Assembly Hall of Shame
#62Re: Assembly Hall of Shame
#63Re: Assembly Hall of Shame
#64Earlier quoted context omitted.
The decoder is an implementation detail that is a subcomponent of NOP; GP was right, and your correction isn't.
It's not an implementation detail, because the decoder runs before the execution of every instruction. If we're going to say that NOP increments IP by one, then we should also say that ADD "stores in dst the addition of src and dst, as well as incrementing IP by the length of the instruction", and JMP imm "increments JMP by imm + the length of the instruction".
ADD does in fact do that.
Re: Assembly Hall of Shame
#65Nop should be #1, because it is infinitely slow for what it does. ;)
It's a little faster than yep.
Re: Assembly Hall of Shame
#66Seems like spam from this creator since there are two things on the front page?
Re: Assembly Hall of Shame
#67Seems like spam from this creator since there are two things on the front page?
submitted by two different people, both with year+ old accounts and decent karma. i dont think either is the author. the other submitter probably read this one, looked at the github, saw something else cool and posted it. (i almost did the same, but bookmarked it instead)
Re: Assembly Hall of Shame
#68Earlier quoted context omitted.
It's not an implementation detail, because the decoder runs before the execution of every instruction. If we're going to say that NOP increments IP by one, then we should also say that ADD "stores in dst the addition of src and dst, as well as incrementing IP by the length of the instruction", and JMP imm "increments JMP by imm + the length of the instruction".
ADD does in fact do that.
I'm not disputing the total effect. I'm asking if you'd rather describe ADD and JMP in this manner, in order to say that NOP does not in fact do nothing.
Re: Assembly Hall of Shame
#69Bus cycles can be arbitrarily long on any processor that has memory cycles with a hand shake requiring an ack, with no timeout.
E.g. we can build a board around a MC68000 where we make it lock up forever in a bus cycle, waiting for a DTACK that doesn't arrive.
Some early microprocessors had clocked bus cycles without handshaking. They would put out an address on some address lines and signal some line together with a read/write indication, and then expect the transfer to be completed within some clock cycles. If nothing is attached to the address, they would read whatever values are on the bus, like maybe all 1's if it is an open drain system that requires the transmitting device to pull to ground to indicate zero.
I'd say that kind of thing belongs to a hall of shame; it requires software hacks to interface with anything that can't keep up with the prescribed bus cycle.
Re: Assembly Hall of Shame
#70[deleted]