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Assembly Hall of Shame

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Re: Assembly Hall of Shame

#51
post #16

Earlier quoted context omitted.

It increments rip by one.

I thought I remembered reading somewhere re: the 8086 microcode disassembly that NOP, which is encoded as XCHG AX,AX actually does run the XCHG microcode and uses an internal scratchpad register to do the exchange.

There were several NOPs - XCHG BX,BX and so on. Those were taken later to be prefixes for new classes of opcodes.

Re: Assembly Hall of Shame

#52
post #6

It’s crazy how computers still seem to get perceivably slow every few years, given how many instructions can be executed in 1ms. Shameful, even.. What’s that law called about programmers wasting all the compute on abstraction?

There are two aspects to compute performance: latency and throughput.

There has been a ton of work to improve throughput, but that's often come at the cost of latency, because a great technique to improve throughput is batching, to avoid the per-task overhead cost.

We've also added many layers of abstraction.

A seminal example is Dan Luu's "computer latency" table (2017) https://danluu.com/input-lag/, which measures the time between a keypress and visible changes on the screen, and wherein an Apple IIe has latency 5x lower than a Lenovo X1 Carbon on Windows.

From some perspective, you could say that the Lenovo on Windows example is an impressive feat of engineering, considering all the subsystems involved (USB, interrupt dispatcher, input layer, windowing system, double-buffering...)

This throughput-over-latency tradeoff can be seen across the entire computer landscape design.

Re: Assembly Hall of Shame

#53

Earlier quoted context omitted.

The new windows notepad is a disgrace

The new mspaint fucked, then unfucked, then refucked my decades-old muscle memory of Win+R mspaint Enter Ctrl+E 1 Tab 1 Enter Ctrl+V to open Paint, resize canvas to minimum, then paste from clipboard. When you press Ctrl+E now, the Units control is selected by default, for some completely asinine reason!!!

You aren't alone in being frustrated by decades of muscle memory being disrespected by MSFT.

Re: Assembly Hall of Shame

#54

Earlier quoted context omitted.

No, that's done by the decoder. It actually does nothing.

I mean....there are several architectures out there which has a nop that is a jump forward. Kind of a tree forest issue imho

I don't know about other architectures in as much detail. I know x86 NOP does nothing.

Re: Assembly Hall of Shame

#56
post #6

It’s crazy how computers still seem to get perceivably slow every few years, given how many instructions can be executed in 1ms. Shameful, even.. What’s that law called about programmers wasting all the compute on abstraction?

Idk man, my computers don't seem to get any slower over time -- no upgrades to any components, either.

Re: Assembly Hall of Shame

#57
post #56
post #6

It’s crazy how computers still seem to get perceivably slow every few years, given how many instructions can be executed in 1ms. Shameful, even.. What’s that law called about programmers wasting all the compute on abstraction?

Idk man, my computers don't seem to get any slower over time -- no upgrades to any components, either.

Does responsiveness get better or worse with updates, in general?

Re: Assembly Hall of Shame

#58
post #15

Related, and linked in the readme: https://github.com/xoreaxeaxeax/smiiiiiiiiiiiiiiii (using the slow instructions to break SMI)

I wish they would just explain it in normal terms instead of this nasty LLM "engaging blog post" style

Chris usually takes an educational angle, I don't think this is LLM-generated content at all it's just his style. I highly encourage watching some of his DefCon or BlackHat talks, they're fun!

Re: Assembly Hall of Shame

#59
post #55

Earlier quoted context omitted.

No, that's done by the decoder. It actually does nothing.

The decoder is an implementation detail that is a subcomponent of NOP; GP was right, and your correction isn't.

It's not an implementation detail, because the decoder runs before the execution of every instruction. If we're going to say that NOP increments IP by one, then we should also say that ADD "stores in dst the addition of src and dst, as well as incrementing IP by the length of the instruction", and JMP imm "increments JMP by imm + the length of the instruction".

Re: Assembly Hall of Shame

#60
post #15

Related, and linked in the readme: https://github.com/xoreaxeaxeax/smiiiiiiiiiiiiiiii (using the slow instructions to break SMI)

I wish they would just explain it in normal terms instead of this nasty LLM "engaging blog post" style

I looked at both links and don't see anything weird or annoying, and I hate overblown styles myself.
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