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I’d recommend the Chenming-Hu books on solar cells and semis available as pdfs on his site. https://www.chu.berkeley.edu/modern-semiconductor-devices-fo... LLMs have already been shown to cause cognitive/skill performance losses in some users. =3 https://www.youtube.com/watch?v=axOcn--n_lM
At my uni, 15 years ago, one postdoc reverse engineered NVIDIA chip and wrote more performant compiler. He did that by connecting oscyloscops to all chip's outputs and started with applying random current on inputs. Using ML and his genius he rediscoverd all opcodes including a few hidden ones. Eventually he got hired by some company that was doing a lot of GPU on supercomputers.
This is absolutely not how reverse engineering a digital logic ASIC works.
Either the story got embellished through retellings, or this person was a fantasist.
There are people who hack on GPUs but it’s done at the software level.
I did get a kick out of imagining a scene where someone is trying to connect an oscilloscope to a circuit board to reverse engineer the CPU opcodes. That’s like the CSI: Miami version of what this would look like.
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To be fair, Ghidra was released in 2019 and in general knowledge was still hard to find even back in 2010 I feel (well, compared to 2026 in the age of AI)
Before that there was, and still is, IDA Pro. Works largely the same but costs a lot, on the order of $1000/seat/year. Useless for hobbyists unless pirated, but reasonable if it's your job. Probably had academic discounts.
Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality. I wish I had more time and I'd throw Calibre at it.
Is there something like an Extract-SPICE tool that takes a circuit and gives you back a text rendering of it ?
Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic). Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so…
Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality. I wish I had more time and I'd throw Calibre at it.
It's even easier in this case because they've included the original verilog source ....
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I’d recommend the Chenming-Hu books on solar cells and semis available as pdfs on his site. https://www.chu.berkeley.edu/modern-semiconductor-devices-fo... LLMs have already been shown to cause cognitive/skill performance losses in some users. =3 https://www.youtube.com/watch?v=axOcn--n_lM
Sorry to interrupt your smugness, but have you actually read that study? It's basically tautological: people remained mostly unfamiliar with code they did not write, and remained mostly unfamiliar with a library they did not use. That's kind of the whole point to begin with! https://homepages.inf.ed.ac.uk/rni/papers/realprg.html
Unless you want to argue that anyone who cannot code is brain damaged, I'd say it's a bit difficult to suggest that this would amount to any kind of clinically relevant cognitive impairment, much to the contrary of the masses desperately hoping and asserting so. Losing a skill you don't use / want / need is very normal cognitive function.
people who can do this stuff are super-smartypants but reminds me how we're going to find out on an industrial level when the Saudis give China some nvidia chips they were grifted they've cloned lots of chips before but nothing that advanced
They weren't trying to steal IBM's design, they already had one of their own, what they wanted to know was "is there any as yet unannounced functionality in the IBM VGA chip?" they didn't want to be caught out when some unknown registers popped up. Of course it turned out there was as yet unannounced functionality - but not by IBM's design, more because of the orthogonality of the design - MODE-X was discovered and became the basis for DOOM's speed, anyone who didn't support it lost out
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Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic). Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so…
yes, but at the transistor level .... it has no idea at that level how those transistors are arranged into gates directly
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Yes. There is exactly that, and we call it an "extraction" tool. It takes a GDS (text representation of shapes in the physical layout), and gives you back a "netlist" (text representation of components and connections in a circuit schematic). Circuit designers use these tools basically daily for two reasons - the first is Layout Versus Schematic. We want to make sure that the physical layout matches the schematic, so…
yes, but at the transistor level .... it has no idea at that level how those transistors are arranged into gates directly