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Nvidia’s Vera Whitepaper Has a Thread Loose

chipsandcheese.com

31–40 of 48 posts

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#31

Let’s not forget the fact that despite their new market cap and being the beneficiary of having a near monopoly on making incredibly complex pickaxes during a gold rush… Nvidia is still the company with a long and consistent history of misleading their customers via marketing. Their greatest hits include: - The digital equivalent of the VW emissions scandal where drivers detected when they were being benchmarked and…

That 4gb vram deal sounds ahead of its time. CPU caches are tiered, why not ram? Looking forward to future systems with 8gb ddr6 and 8gb ddr5. "Swapping to ram" would become a thing.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#33
post #14

Earlier quoted context omitted.

Death of Itanium was that it was a) VLIW and b) Intel was too arrogant. So it went to the same destination as later Larrabee and ATI/AMD attempts at VLIW GPUs. That is, nowhere. Also you are wrong and anyone sizing up an arch to put their loads onto must first try that load on it and not rely on "bah, compilers compile on it".

VLIW works for DSP applications, it's not an instant dead end. It's a good fit in cases where code path and memory accesses are predictable, like shader code.

Essentially every cell phone out there has a VLIW DSP like Qualcomm's Hexagon cores (though AFAIK Qualcomm is the only one who lets you run your on programs on their DSP).

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#34
post #11

In today’s “agentic” world, everyone seems to have forgotten approximately everything we used to know about security. And this new CPU is going all in on value speculation. Delightful. Maybe if “cyber” models get good enough at exploiting speculation attacks, people will start demanding equipment that is less prone to these attacks.

I think security is going to get devalued in the near future. The safest strategy is going to be to need as little as possible of the stuff that you need to keep secret. And you won't keep that stuff on a device that is shared in any manner, or maybe even connected anywhere.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#35
post #28
post #21

Earlier quoted context omitted.

In a hypothetical world where AMD wasn't allowed to do AMD64, and Intel stayed committed to Itanium: Itanium would still have sucked, and both PowerPC and SPARC would have out-sold Itanium by an even wider margin than they did in this reality. Itanium could only have succeeded if AMD64 wasn't possible and literally all of the competing 64-bit architectures were killed off by their owners so they could jump on the Ita…

Except you would never had Windows running on either PowerPC and SPARC. Remember, the very first Windows XP 64 bit release was on Itanium.

Windows NT on PowerPC was an actual product, although running in 32-bit mode.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#36
post #21
post #18

Earlier quoted context omitted.

Itanium only died because AMD exists, and due to various licensing reasons they were allowed to come up with AMD64.

In a hypothetical world where AMD wasn't allowed to do AMD64, and Intel stayed committed to Itanium: Itanium would still have sucked, and both PowerPC and SPARC would have out-sold Itanium by an even wider margin than they did in this reality. Itanium could only have succeeded if AMD64 wasn't possible and literally all of the competing 64-bit architectures were killed off by their owners so they could jump on the Ita…

> Itanium would still have sucked

I'm not completely convinced of this.

If you ignore VLIW, you just have a very unexciting RISC ISA, but because of the VLIW, you get extra scheduling info that most RISC designs don't provide which might be advantageous. The real question is actually about the code density of 41-bit instructions and if it can be offset by the 128-bit package (and perhaps something like allowing new 24-bit compressed instructions).

Poulson already somewhat proved part of this as it added back a traditional frontend and even added some OoO capabilities and 4-way SMT. It wasn't earth-shattering, but it wasn't absolute garbage either.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#37
post #29
post #11

In today’s “agentic” world, everyone seems to have forgotten approximately everything we used to know about security. And this new CPU is going all in on value speculation. Delightful. Maybe if “cyber” models get good enough at exploiting speculation attacks, people will start demanding equipment that is less prone to these attacks.

aarch64 has a CPU mode, DIT (Data Independent Timing), specifically for allowing software to request all fancy value prediction stuff to be disabled for the duration of processing of sensitive data. (doesn't help when the attack target is general-purpose/user-controlled code leaking things, but if you're relying on a process not leaking memory plainly available to it without full careful control of what the process r…

No way, ARM screwed this up less than Intel and at least allows user code to access the control bit. Intel’s equivalent, DOITM, is not accessible at CPL3.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#38
I did appreciate the article and it's not AI slop by any means, but did anyone else notice how the language and grammar felt very LLM-written? Or at least edited from a LLM draft?

I used to really enjoy Chips and Cheese's writing, not sure if they made a change.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#39
post #28
post #21

Earlier quoted context omitted.

In a hypothetical world where AMD wasn't allowed to do AMD64, and Intel stayed committed to Itanium: Itanium would still have sucked, and both PowerPC and SPARC would have out-sold Itanium by an even wider margin than they did in this reality. Itanium could only have succeeded if AMD64 wasn't possible and literally all of the competing 64-bit architectures were killed off by their owners so they could jump on the Ita…

Except you would never had Windows running on either PowerPC and SPARC. Remember, the very first Windows XP 64 bit release was on Itanium.

Um...while not "OG Windows" I guess, PowerPC was an officially supported and shipping Windows NT 3.51 & 4 target[1]. It was released a couple of years before XP 64-bit for itanic. SPARC was a planned NT port, and while it never happened, it could have[2][3].

[1] https://archive.org/details/NT351PMZPPC

[2] https://www.techmonitor.ai/technology/undercurrent_bubbling_...

[3] Legend has it that the SPARC port existed, done by Intergraph, but for Reasons was never a product.

Re: Nvidia’s Vera Whitepaper Has a Thread Loose

#40

Let’s not forget the fact that despite their new market cap and being the beneficiary of having a near monopoly on making incredibly complex pickaxes during a gold rush… Nvidia is still the company with a long and consistent history of misleading their customers via marketing. Their greatest hits include: - The digital equivalent of the VW emissions scandal where drivers detected when they were being benchmarked and…

That 4gb vram deal sounds ahead of its time. CPU caches are tiered, why not ram? Looking forward to future systems with 8gb ddr6 and 8gb ddr5. "Swapping to ram" would become a thing.

There are lots of platforms where RAM is tiered, and operating systems that support it. For example, CLX allows for a "NUMA node without CPU" abstraction; there was a HN article recently about Facebook cooking up their own silicon and Linux patches to implement this so they could expand DDR5 platforms with retired DDR4 memory. Not a new idea...20+ years ago I used mc68k & ns32k BSD systems that had a couple of meg of fast memory onboard and more, slower memory hung off a VMEBus. System tried to keep hot pages in fast memory and it worked reasonably well.
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