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Designing an Ethernet Switch ASIC

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Re: Designing an Ethernet Switch ASIC

#21

Post by tuetuopay »

sophacles wrote: post #11
noncoml wrote: post #2

“ Cut-through vs Store-and-Forward” I had a Google interview collapse because the last interviewer was a Principle Engineer who just couldn’t accept that a switch will ever forward a frame before reading in full and checking the FCS. I was too much of an idiot to go along with it and instead ended up having an argument with him.

I'm struggling to think of any real-world networking scenario where cut-through switching for ethernet can provide any sort of benefit. Most data-center networks are involve aggregation/spine/core switches at higher speed than TOR/leaf switches - so the packet has to be buffered. Most every workload is going to involve port collisions (2 packets at the same time needing the same output port) - again a full buffering…

The two scenarios I can think of that definitely make use of cut-through are timekeeping systems, and HFT. The latter goes even further, where the switches at the exchange do cut-through, but also ensure the packet is broadcast to multiple ports at the exact same time. This is done so that no specific HFT firm get an advantage from being on port 10 rather than port 20. They even measure out the outgoing fibers to be the same length.

Re: Designing an Ethernet Switch ASIC

#22

Post by random__duck »

zrobotics wrote: post #19

This is extremely cool, I've played with FPGA design but never really even looked into custom ASIC design due to budget concerns. I hadn't heard of the tinytapeout project. Any recommended links for getting started? I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly…

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)

I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.

Re: Designing an Ethernet Switch ASIC

#23

Post by toast0 »

random__duck wrote: post #22
zrobotics wrote: post #19

This is extremely cool, I've played with FPGA design but never really even looked into custom ASIC design due to budget concerns. I hadn't heard of the tinytapeout project. Any recommended links for getting started? I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly…

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" ( https://talesonthewire.com/projects/until_heat_death_do_us_p... ) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :) I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_…

> So for everyone else also running multiple instances of experimental hardware on their local network I have added an additional 2 Byte magic number using the all so original 0xCAFE (little endian) allowing packet parsers to distinguish between this ASIC’s experimental traffic and your other experimental traffic.

Just saying, it's good form to do network stuff in big endian. Although since it's already done I dunno how hard you should work to retcon that to 0xFECA...

Re: Designing an Ethernet Switch ASIC

#24

Post by jandrese »

That memory constraint is a real killer on the chip, even one that is a first generation toy like this. Only having 4 entries in the forwarding table is going to be an immediate problem if that switch is ever connected to another switch.

I wonder if it wouldn't make sense for one of the ports to be designated the "uplink" port and if the switch receives a packet destined for something not in the table it forwards it out the uplink port so long as the packet did not arrive via that port. It could even save a bit of memory by not storing entries for the uplink port in the table.

Re: Designing an Ethernet Switch ASIC

#25

Post by Taniwha »

jandrese wrote: post #24

That memory constraint is a real killer on the chip, even one that is a first generation toy like this. Only having 4 entries in the forwarding table is going to be an immediate problem if that switch is ever connected to another switch. I wonder if it wouldn't make sense for one of the ports to be designated the "uplink" port and if the switch receives a packet destined for something not in the table it forwards it…

On TinyTapeout you can add more tiles up to 16 times the size of this (at which point you likely jump to waferspace)

Re: Designing an Ethernet Switch ASIC

#26

Post by stinkbeetle »

icedchai wrote: post #14
noncoml wrote: post #12

Earlier quoted context omitted.

> but rather, was refusing to accept that the scenario they're talking through with you would ever involve an effectively deployed cut-through switch (since that's basically never). Nope, the argument was exactly if a cut-through switch exists or ever existed Edit: Actually the conversation came back to me: He asked me about the frame format. Once I drew that on the board, he asked why is the DST before the SRC. My a…

So he didn't want to google it?

I see you've never had a run-in with a blowhard in a position of power. Lucky.

Re: Designing an Ethernet Switch ASIC

#27

Post by inigyou »

zrobotics wrote: post #19

This is extremely cool, I've played with FPGA design but never really even looked into custom ASIC design due to budget concerns. I hadn't heard of the tinytapeout project. Any recommended links for getting started? I have a (really dumb, kinda meme-y) project involving a dead hakko soldering iron and "Internet of Soldering", a custom ASIC for the actual front-end would be the appropriate level of silly and possibly…

Tiny Tapeout has its own guide for getting started

Re: Designing an Ethernet Switch ASIC

#28

Post by inigyou »

toast0 wrote: post #23
random__duck wrote: post #22

Earlier quoted context omitted.

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" ( https://talesonthewire.com/projects/until_heat_death_do_us_p... ) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :) I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_…

> So for everyone else also running multiple instances of experimental hardware on their local network I have added an additional 2 Byte magic number using the all so original 0xCAFE (little endian) allowing packet parsers to distinguish between this ASIC’s experimental traffic and your other experimental traffic. Just saying, it's good form to do network stuff in big endian. Although since it's already done I dunno…

If your 0xCAFE gives you a 0xFECA1A55, stop going there...

Re: Designing an Ethernet Switch ASIC

#29

Post by inigyou »

jandrese wrote: post #24

That memory constraint is a real killer on the chip, even one that is a first generation toy like this. Only having 4 entries in the forwarding table is going to be an immediate problem if that switch is ever connected to another switch. I wonder if it wouldn't make sense for one of the ports to be designated the "uplink" port and if the switch receives a packet destined for something not in the table it forwards it…

Correct ethernet switch behavior forwards a packet to all ports if the destination MAC is unknown

Re: Designing an Ethernet Switch ASIC

#30

Post by inigyou »

icedchai wrote: post #14
noncoml wrote: post #12

Earlier quoted context omitted.

> but rather, was refusing to accept that the scenario they're talking through with you would ever involve an effectively deployed cut-through switch (since that's basically never). Nope, the argument was exactly if a cut-through switch exists or ever existed Edit: Actually the conversation came back to me: He asked me about the frame format. Once I drew that on the board, he asked why is the DST before the SRC. My a…

So he didn't want to google it?

If you Google it, you find many copies of theory, but not a single reference to a cut-through switch ever existing in real life.
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