Scrying the AMD GFX1250 LLVM Tea Leaves
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Scrying the AMD GFX1250 LLVM Tea Leaves
1–10 of 11 posts
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#2...not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache.
What is this feature for? When do you need it?
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#3... not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache. What is this feature for? When do you need it?
GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP)
I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time.
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#4I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#5Where does someone start on kernel development for an RDNA4? Books, resources, whatever?
8 year developer just getting into to AI side of the house
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#6I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.
I'm very interested in your use case.
I looked into bit-slicing techniques, but they increase throughput at the cost of massive latency. This is not acceptable for realtime audio.
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#7... not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache. What is this feature for? When do you need it?
GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP) I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time.
sure, but what kind?
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#8Earlier quoted context omitted.
GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP) I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time.
sure, but what kind?
wait/arrive seems obvious to me. So I'll talk about that... As a synchronization primitive, its very useful for things like:
parallel_memset(data, 0); // The 1024 threads go off and, in parallel + some efficient manner, initialize the datastructure
barrier(); // wait for all 1024 threads to reach here before continuing.
do_stuff(); // This probably relies on all default data being set before starting
Cluster arrive + Cluster wait allow for you to split the barrier into two units. Maybe the first half of a loop must be synchronized, but there's "spare extra work" you can do before calling wait(). This likely makes threading smoother.
parallel_memset(data, 0); // The 1024 threads go off and, in parallel + some efficient manner, initialize the datastructure
arrive();
do_spare_work(); // some extra work before checking for a wait
wait(); // We ran out of main work + spare work, so now we must fully stop and wait
do_stuff(); // This probably relies on all default data being set before starting
---------
As far as the L2 cache thing specifically: I don't know.
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#9I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.
I'm very interested in your use case. I looked into bit-slicing techniques, but they increase throughput at the cost of massive latency. This is not acceptable for realtime audio.
Fusing multiple boolean logic functions into one.
Re: Scrying the AMD GFX1250 LLVM Tea Leaves
#10I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.
They already do, it's called v_bitop3_b32. Added in CDNA4, present in CDNA5 and will be making its way in RDNA5, if the LLVM code is to be trusted.
https://www.amd.com/content/dam/amd/en/documents/instinct-te...