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RISC-V Is Inevitable: State of the Union Keynote Argues

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Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#81

Post by leoc »

sph wrote: post #39
mort96 wrote: post #35

Earlier quoted context omitted.

I haven't exactly seen an outpouring of consumer demand for CHERI.

Is there an outpouring of hardware offer for CHERI? I'm a random nobody, but I'm sitting on this design for a message-passing platform that can only truly perform in a world where processes live in a single address space, which requires CHERI hardware to be feasible (or secure) at all. CHERI would open many doors in operating system design and security, and it's stagnant because it's not a real thing yet, there's no…

Right: it's not clear whether the availability of some $300 US CHERI SBCs would be enough to carry CHERI to glory, but it would obviously generate a significant pop of awareness, support and grassroots activity. For their part the antis could then transition seamlessly from "nobody wants it lol" to "all these enthusiasts are so annoying and out of touch with reality lol" as is traditional. Instead, AFAICT, the CHERI leadership seems to be convinced that the next step is to present the business case for CHERI to people at or just below CxO level https://www.youtube.com/watch?v=FJhS2i7KVtI . Imagine how far Rust (or, earlier and further afield, Linux) adoption would have got if it had relied solely on having an academic-led consortium present a business case to CxOs, instead of being pushed along by internal pressure from mid-level technical staff who had used it themselves and were crazy about it.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#82

Post by snvzz »

modulovalue wrote: post #8

I'm working on making SIMD better in Dart. Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I don't really plan to look into it at all. This is mostly because their approach to SIMD is so different, but also because I can't test it at all. Are there any RISC-V "machines"? that one can use to do…

>Are there any RISC-V "machines"? that one can use to do something useful or fun with that someone here could recommend?

Multiple boards based on the RVA23 spacemiT K3 are shipping as of recently.

They are usefully performant. Comfortable webbrowsing and playing 4K youtube without issues sort of fast.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#83

Post by ak_111 »

speed_spread wrote: post #49
thrownawaysz wrote: post #40

If we go by Apple's architecture history we will get a new one, maybe RISC-V, in 2036. m68k (1984) > PPC (1994) - 10 years PPC (1994) > x86 (2006) - 12 years x86 (2006) > ARM64 (2020) - 14 years ARM64 (2020) > ??? (2036) - 16 years

Except that ARM is pretty much theirs, or at least they have complete control over it, which they never did for any previous arch. They also handle chip production directly. Nothing in RISC-V could be worth more than what they can already wring out of ARM without having to migrate.

ten years is a very long time in technology, RISC-V ecosystem could be so vibrant and advanced that it might prove more cost effective for Apple just to feed off it (assuming Apple is still relevant by then).

It's almost like trying to predict if the smartphone leaders in 2006 (Nokia / RIM) would want to adopt this new mobile operating system that hardly anyone uses (android) in 2016.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#84

Post by snvzz »

ltbarcly3 wrote: post #65

Why can't anyone build a performant RISC-V cpu? The SpacemiT K3 seems to be the fastest available right now, and it's basically a joke. https://www.phoronix.com/review/spacemit-k3-pico-itx/3 I'm starting to get the feeling that there is something fundamentally broken in the RISC-V specification that fundamentally limits performance.

>and it's basically a joke.

Look up the fab process node and die area of that chip, and think again.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#85

Post by hmry »

rzerowan wrote: post #76
PaulRobinson wrote: post #67

Headline could read: "RISC-V adoption is 'inevitable' according to RISC-V advocate at RISC-V conference to people who are invested in RISC-V who had come to hear about state of RISC-V adoption". I'm curious where the data is to support the argument. I am struggling to see the adoption appetite outside of niche applications where licensing costs of existing architectures are a key barrier.

I believe in microcontrollers its already pretty ubiquitous , see their utilisation by WesternDigital with their SwerV core thats already shipping since 2019. At speeds and complexity comparable to desktop/server cores from Intel/AMD they are still lagging in perf though improving as more cores get deployed. Also to add into the mix the whole geopolitics with non-US players hedging. So potential is there will just de…

Non-US hedging will be big for RISC-V in the future, but the geopolitics can also cut the other way. E.g. US banning US companies from using Chinese RISC-V chips, to protect their domestic players. Especially now that intel is partially state-owned.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#87

Post by sylware »

Everything pushing forward RISC-V is a good thing (this time I get it right...)

I code RISC-V assembly almost everyday, beyond the major point that it is a NON-IP-LOCKED ISA (unlike arm and x86-64), it feels like it does 'sweet spot' nearly all the time. Namely, I am more into binary specifications which means, if RISC-V is zapped one day, we still have some RISC-V byte code and port to an IP-LOCKED ISA is reasonable.

The hard part: _really performant_ micro-architectures for server/desktop/embedded/mobile on latest silicon process.

The harder part: getting much binary-only 'critical' software running there (for instance desktop video games).

And the super hard part: big mistakes _will be made_, and it is going to hurt ooofely.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#88

Post by invokestatic »

rzerowan wrote: post #76
PaulRobinson wrote: post #67

Headline could read: "RISC-V adoption is 'inevitable' according to RISC-V advocate at RISC-V conference to people who are invested in RISC-V who had come to hear about state of RISC-V adoption". I'm curious where the data is to support the argument. I am struggling to see the adoption appetite outside of niche applications where licensing costs of existing architectures are a key barrier.

I believe in microcontrollers its already pretty ubiquitous , see their utilisation by WesternDigital with their SwerV core thats already shipping since 2019. At speeds and complexity comparable to desktop/server cores from Intel/AMD they are still lagging in perf though improving as more cores get deployed. Also to add into the mix the whole geopolitics with non-US players hedging. So potential is there will just de…

Firmware & systems dev here, ARM still dominates in the microcontroller space. There are some niche offerings from major vendors but again they are niche. Espressif is the sole exception with their newer ESP32-C series chips, but they can get away with it due to their massive HAL. ARM Cortex is still the standard because there’s a decade or two of inertia behind it.

An apt comparison would be C vs Rust. Yes, Rust may be growing in market share, but C still dominates.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#89

Post by ACCount37 »

PaulRobinson wrote: post #67

Headline could read: "RISC-V adoption is 'inevitable' according to RISC-V advocate at RISC-V conference to people who are invested in RISC-V who had come to hear about state of RISC-V adoption". I'm curious where the data is to support the argument. I am struggling to see the adoption appetite outside of niche applications where licensing costs of existing architectures are a key barrier.

Currently, RISC-V actively shows up in embedded - especially "deep embedded" like specialized ASICs with embedded MCU cores.

It's often seen displacing things like 8051, ARM Cortex-M0, ARC/ARCompact, Xtensa and oddball fully custom cores.

It also starts to show up in low end Linux SoCs - often, again, purpose-specific ones, like SoCs for IP cameras or other single purpose consumer electronics like robot vacuums and drones.

None of those are sexy "high end" applications, like laptops or smartphones, but the adoption is real.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#90

Post by leoc »

pjmlp wrote: post #72
sph wrote: post #39

Earlier quoted context omitted.

Is there an outpouring of hardware offer for CHERI? I'm a random nobody, but I'm sitting on this design for a message-passing platform that can only truly perform in a world where processes live in a single address space, which requires CHERI hardware to be feasible (or secure) at all. CHERI would open many doors in operating system design and security, and it's stagnant because it's not a real thing yet, there's no…

Tell ARM about it, https://cheri-alliance.org/discover-cheri/cheri-products/mor...

It's a lot better than things apparently used to be, but what CHERI really needs to develop a grassroots is a board that runs CheriBSD ( https://www.cheribsd.org/ ) and is actually available for a few hundred US dollars cash down, not a board of which you can apply to, maybe, have a single unit eventually allocated to you if you are deemed worthy. Even taking for granted that they only have a small supply which has to be allocated on a non-commercial basis for now, they should be beating down the doors of guys like Jeff Geerling and Wendell Wilson from Level1Techs and thrusting eval boards in their hands, not sitting on their throne waiting to hear entreaties.
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