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OpenAI unveils its first custom chip, built by Broadcom

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Re: OpenAI unveils its first custom chip, built by Broadcom

#261

Post by Planktonne »

NitpickLawyer wrote: post #198
xnx wrote: post #160

Earlier quoted context omitted.

Impossible to know. Could be fake/aspirational roles to impress investors with their grand vision.

Jesus. This is tinfoil hat territory now. Why would they fake something like that? ANY company in this field would try to become free from nvda. Goog has done it already, amazon has their own thing, so it can be done. Not saying they'll 0shot this vertical, but ffs, they don't need to fake anything. They are making an effort, and it would be insane to think they aren't. Might work, might not work, but to even think t…

They have a history of lying and making grandiose claims. It's unreasonable to extend them the benefit of the doubt again.

Re: OpenAI unveils its first custom chip, built by Broadcom

#262

Post by signatoremo »

I haven't seen this discussed here:

So far, the accelerator is showing cost savings of roughly 50% compared with typical AI graphics processing units, Broadcom Chief Executive Officer Hock Tan said in an interview. - [0]

50% cost saving. The picture changes so quickly, there are still a lot of low hanging fruits, that I find any discussion about whether a vendor has moats, or if they can recoup investment, is moot and futile.

[0] - https://www.bloomberg.com/news/articles/2026-06-24/openai-an...

Re: OpenAI unveils its first custom chip, built by Broadcom

#263

Post by cactusplant7374 »

maz1b wrote: post #5

Pretty huge move. Google and their TPUs are looking infinitely more prescient as I think they are on their 7th generation, along with the offshoots it inspired like the LPU and even others, perhaps like Cerebras and their Wafer Scale Engine. However, based off first impressions, it seems like this is meant for inference side, and not training, which is also an interesting choice.

Cerebras's Codex Spark 5.3 has been a huge flop. Small context window and old model. But hopefully they can improve so that we can benefit from 1000 tokens/second with GPT 5.5.

Re: OpenAI unveils its first custom chip, built by Broadcom

#264

Post by zgao »

otterdude wrote: post #176
zgao wrote: post #125

Earlier quoted context omitted.

Chip CEO here. It really depends on what "design" or "production" means. Does "design" mean that the design was complete? Does "production" mean the beginning of production, i.e. tapeout? If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. If measuring from concept (no RTL at all, block diagram o…

Not a chip CEO, but I read this article and thought that they're working on some kind of application specific chip only for serving models. Similar to how an FPGA can optimize certain tasks. Given constant weights / biases of a Transformer / DNN you could use pipelining to feed forward calculations through the array one layer at a time. For DNN's with thousands of layers you might see 1:1 speed up per layer channel.…

Yes, my statement was not about the quality or performance of the chip -- simply the tapeout timeline that was stated, by itself.

Re: OpenAI unveils its first custom chip, built by Broadcom

#265

Post by y1n0 »

knicholes wrote: post #147
Aurornis wrote: post #136

Earlier quoted context omitted.

> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. PCB design and 3D CAD design are different topics. Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog

Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?

For digital chip design, research Verilog and/or SystemVerilog, and for tools, check out verilator and the OSS cad suite: https://github.com/YosysHQ/oss-cad-suite-build

Re: OpenAI unveils its first custom chip, built by Broadcom

#266

Post by zgao »

nonethewiser wrote: post #162
zgao wrote: post #125

Earlier quoted context omitted.

Chip CEO here. It really depends on what "design" or "production" means. Does "design" mean that the design was complete? Does "production" mean the beginning of production, i.e. tapeout? If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. If measuring from concept (no RTL at all, block diagram o…

>If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. Even for a company’s first design?

The typical way a chip effort in a non-chip company works is that the "design" is the RTL (e.g. SystemVerilog that defines the behavior of the chip) and then this is handed off to a third-party "design house" (such as Broadcom) that turns that code into a real image of a chip, which is called a GDS (basically you can think of this as a very big layer by layer photoshop file) that can actually be sent to a fab. This is called "backend design", in contrast to the "frontend design" (the RTL itself).

As another commenter said, Broadcom is very experienced with backend design (as well as the supply chain management, testing, etc. that comes after the chip is taped out) and so this can't be regarded as a "first chip". Richard Ho (the head of hardware at OpenAI) is also extremely experienced and used to be the head of the Google TPU effort -- where he actually worked with Broadcom in a similar tapeout already. So yes, this is not a "first design"!

Re: OpenAI unveils its first custom chip, built by Broadcom

#267

Post by londons_explore »

Smaug123 wrote: post #210
londons_explore wrote: post #192

I wanna see an inference chip where the weights are part of the rom of the chip. There would be 1 multiplier per weight (and since they're constant, the whole thing turns into a bunch of simple adders), and the total pipelined system throughput would be one token per clock cycle. That means you can probably have millions of users simultaneously using a single bit of silicon, with perhaps 500 million tokens per second…

By the way, you've seen Cerebras? It's not gone as far as what you described - loads of cores and RAM but you still load up the weights onto it as software and they need to be streamed into the chip for large models - but it is a whole wafer.

There is a huge downside to weights being modifiable - it means you need to have multipliers (not simply adders), and SRAM to store those weights.

I suspect for equal performance, that's probably a 5x increase in silicon area (and therefore cost).

Re: OpenAI unveils its first custom chip, built by Broadcom

#269

Post by cpldcpu »

smetannik wrote: post #172
cpldcpu wrote: post #170

I had Opus 4.5 design an LLM inference engine in verilog, including firmware and automated verification a while ago: https://github.com/cpldcpu/smollm.c It's of course far from optical. But lowering the implementation through the abstraction levels turned out to be extremely powerful.

Can you suggest some tutorials for Verilog and FPGAs in general? I have a spare Tang Nano 9k but I don't feel confident about blindly asking Claude to vibecode me a solution and still would like to have at-least a basic level of understanding.

hm.. has been quite a while for me. The good thing about the Tang Nano is that it is supported by the Yosys open source toolchain. There are quite a few resources on the web when you search for the combination.

Re: OpenAI unveils its first custom chip, built by Broadcom

#270

Post by wmf »

signatoremo wrote: post #262

I haven't seen this discussed here: So far, the accelerator is showing cost savings of roughly 50% compared with typical AI graphics processing units, Broadcom Chief Executive Officer Hock Tan said in an interview. - [0] 50% cost saving. The picture changes so quickly, there are still a lot of low hanging fruits, that I find any discussion about whether a vendor has moats, or if they can recoup investment, is moot an…

If GPUs have 75% margin then 50% cheaper is no surprise.
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