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OpenAI unveils its first custom chip, built by Broadcom

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Re: OpenAI unveils its first custom chip, built by Broadcom

#171

Post by formerly_proven »

nonethewiser wrote: post #162
zgao wrote: post #125

Earlier quoted context omitted.

Chip CEO here. It really depends on what "design" or "production" means. Does "design" mean that the design was complete? Does "production" mean the beginning of production, i.e. tapeout? If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. If measuring from concept (no RTL at all, block diagram o…

>If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. Even for a company’s first design?

This isn't Broadcom's first design.

Re: OpenAI unveils its first custom chip, built by Broadcom

#172

Post by smetannik »

cpldcpu wrote: post #170

I had Opus 4.5 design an LLM inference engine in verilog, including firmware and automated verification a while ago: https://github.com/cpldcpu/smollm.c It's of course far from optical. But lowering the implementation through the abstraction levels turned out to be extremely powerful.

Can you suggest some tutorials for Verilog and FPGAs in general?

I have a spare Tang Nano 9k but I don't feel confident about blindly asking Claude to vibecode me a solution and still would like to have at-least a basic level of understanding.

Re: OpenAI unveils its first custom chip, built by Broadcom

#173

Post by giancarlostoro »

knicholes wrote: post #147
Aurornis wrote: post #136

Earlier quoted context omitted.

> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. PCB design and 3D CAD design are different topics. Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog

Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?

You're comparing apples and oranges.

Re: OpenAI unveils its first custom chip, built by Broadcom

#175

Post by quadrature »

knicholes wrote: post #147
Aurornis wrote: post #136

Earlier quoted context omitted.

> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. PCB design and 3D CAD design are different topics. Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog

Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?

VHDL is not a language for spatial design. Its more akin to a programming language with circuit semantics.

Re: OpenAI unveils its first custom chip, built by Broadcom

#176

Post by otterdude »

zgao wrote: post #125
sharkjacobs wrote: post #61

> Developed from design to production in nine months, accelerated by OpenAI’s models > the use of OpenAI models to accelerate parts of the design and optimization process. I wish there was more about this. As is I kind of have to assume that this is just meaningless marketing, like saying development was accelerated by Microsoft Office or their 5k LG Ultrafine 40-inch monitors. Like, if this was as big a deal as it k…

Chip CEO here. It really depends on what "design" or "production" means. Does "design" mean that the design was complete? Does "production" mean the beginning of production, i.e. tapeout? If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. If measuring from concept (no RTL at all, block diagram o…

Not a chip CEO, but I read this article and thought that they're working on some kind of application specific chip only for serving models. Similar to how an FPGA can optimize certain tasks.

Given constant weights / biases of a Transformer / DNN you could use pipelining to feed forward calculations through the array one layer at a time. For DNN's with thousands of layers you might see 1:1 speed up per layer channel.

I doubt they would undergo this process for marginal gains.

Re: OpenAI unveils its first custom chip, built by Broadcom

#177

Post by DoctorOetker »

fecal_henge wrote: post #123
FanaHOVA wrote: post #76

Earlier quoted context omitted.

NVIDIA already designs most of their chips using AI. Why would you assume it's meaningless marketing?

Perhaps because they are suggesting what they are doing is novel.

novel to whom, the reader or the industry?

something can be non-novel in the industry, yet novel to the reader, at which point it is useful ... for such readers.

Re: OpenAI unveils its first custom chip, built by Broadcom

#178

Post by KeplerBoy »

HarHarVeryFunny wrote: post #38
theowaway213456 wrote: post #27

This seems like more competition for Cerebras? Am I understanding correctly?

This is just an uncut wafer - I don't think it's intended to be a wafer-scale chip. Cerebras etch memory onto the wafer alongside the processing elements, but AFAIK OpenAI are going to be using HBM memory and a conventional chiplet design.

Still competition for cerebras. Seems quite unlikely they will get an OpenAI deal anytime soon.

Re: OpenAI unveils its first custom chip, built by Broadcom

#180

Post by HarHarVeryFunny »

sharkjacobs wrote: post #61

> Developed from design to production in nine months, accelerated by OpenAI’s models > the use of OpenAI models to accelerate parts of the design and optimization process. I wish there was more about this. As is I kind of have to assume that this is just meaningless marketing, like saying development was accelerated by Microsoft Office or their 5k LG Ultrafine 40-inch monitors. Like, if this was as big a deal as it k…

I would assume they've already made as big a deal of it as they can without outright lying too much. Read the rest of the press release.

FWIW, Google is now on their 8th generation TPU, having put out the last 4 generations on a 1-year cadence.

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