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Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

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Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#11

Post by kens »

tasty_freeze wrote: post #6

Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no d…

That's a very interesting board! It came out in 1976 (four years before the 8087) and cost $499 assembled, equivalent to $2900 in current dollars, so it was expensive. It was really a decimal processor built from simple TTL parts, and had four microcoded instructions: add, subtract, multiply, and divide. Arithmetic used the 74LS181, the very popular ALU chip. (It did multiplication with repeated addition; there's no ROM with digit products, unless that was a later version.) The "small RAM" was very small by modern standards: four 4-bit registers that each held 16 digits. Each register was implemented with a 74S189 chip.

The microcode is available, so it would be a fun project to write a simulator that runs the microcode.

Manual and schematics are here if anyone is looking for them: https://bitsavers.org/pdf/northstar/boards/North_Star_Floati...

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#14

Post by tasty_freeze »

kens wrote: post #11
tasty_freeze wrote: post #6

Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no d…

That's a very interesting board! It came out in 1976 (four years before the 8087) and cost $499 assembled, equivalent to $2900 in current dollars, so it was expensive. It was really a decimal processor built from simple TTL parts, and had four microcoded instructions: add, subtract, multiply, and divide. Arithmetic used the 74LS181, the very popular ALU chip. (It did multiplication with repeated addition; there's no…

My mistake -- what I wrote was from memory so I got the bit wrong about the multiplier ROM. I must have confused that detail with the design of the Wang 2200 computer, which had double precision BCD float math and did in fact have a 4b x 4b multiplier ROM.

https://www.wang2200.org/

(I'm the guy behind the wang2200.org domain)

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#15

Post by SyzygyRhythm »

Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input.

The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#16

Post by kens »

SyzygyRhythm wrote: post #15

Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input. The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?

Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits).

If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifters. I don't know how the circuit area compares between the two approaches--two more complex stages vs six simpler stages--but I suspect the two-stage approach wins.

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#18

Post by xenadu02 »

kens wrote: post #16
SyzygyRhythm wrote: post #15

Why isn't the shifter built with a log2 arrangement, shifting 32-16-8-4-2-1 bits? Takes fewer sub-stages and doesn't require a separate decoder for the input. The article mentions it already has a two-stage design, shifting bits and then bytes, so it can't be about shifting more than one bit at a time. Anyone know why?

Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits). If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifte…

Wasn't this also one of the last chips laid out by hand (literally the masks were cut and laid out physically)? Or am I thinking of something else?

I sometimes wonder if some design decisions were made on that basis.

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#19

Post by kjs3 »

tasty_freeze wrote: post #6

Northstar made an S-100 card which did FP math, using BCD arithmetic. It had a ucode ROM and a 4b (single digit) ALU, and a few small RAMs to hold the digits. If I remember correctly you could program it to select how many digits you wanted in your representation, up to 14 digits. It did everything one digit at a time, and it had a 256 byte ROM to carry out any digit*digit product in one cycle. For normalization no d…

I didn't know about that board; very cool. Northstar had an S-100 'math board' bases on an AMD 9511 FP chip that was popular in some very niche markets. Quite a bit more capable, but probably not as intrinsically interesting.

Re: Die analysis of the 8087 math coprocessor's fast bit shifter (2020)

#20

Post by kens »

xenadu02 wrote: post #18
kens wrote: post #16

Earlier quoted context omitted.

Yes, you can use a "logarithmic shifter". The CDC 6600 supercomputer (1964) used that approach. The tradeoff is that you need more stages with the logarithmic approach (six versus two for 64 bits). If you're using MOS pass transistors for each stage, you lose some voltage at each stage, which limits the number of stages. I think this is why the 8087 (and the 386) used two-stage shifters rather than logarithmic shifte…

Wasn't this also one of the last chips laid out by hand (literally the masks were cut and laid out physically)? Or am I thinking of something else? I sometimes wonder if some design decisions were made on that basis.

CAD was a very incremental process. Early chips were drawn by hand and the Rubylith masks were cut by hand with the help of a Coordinatograph. Later, Intel used a Xynetics plotter to cut the Rubylith. By 1974, layouts were digitized with a Calma GDS I so repeated cells could be handled automatically. By the time of the 8087, there was a lot of automation.

You might think that the 8087's shifter would be a regular grid, easy to lay out by hand. It turns out to be very optimized and irregular. (I traced it out by hand and it was a pain.)

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