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This is really nice for competition in semiconductor manufacturing. The TSMC quasi-monopoly (with Samsung fabs slightly lagging) and limited capacity is not good for the market. Owning leading edge fabs might also help Intel to keep up the competition in the x86 market. Intel is the underdog now!
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"Big if true". That's surprising. More ASML machines = more capacity in the future. Do you have a source for that? Intel would need to have lots of (and / or very big) customers lined up or big plans to manufacture possibly more than CPUs of their own design to make use of that capacity.
They mention that Intel bought the initial production run in the page that introduced the new product. > can print transistors 1.7 times smaller – and therefore achieve transistor densities 2.9 times higher – than they can with NXE systems. https://www.asml.com/en/news/stories/2024/5-things-high-na-e...
Big deal, smart for all parties, really. Apple standards will make Intel step up and become a better foundry partner. Apple will gain increasingly needed diversification. US supply chain gets a boost. Should be fine for TSMC in the short to medium term. Apple not going to risk actual mainline iPhone SoC on Intel any time soon, so lion share of TSMC Apple revenue will be fine.
The biggest reason to do this is because TSMC's N2 node and future nodes will be dominated by AI chips. Since AI chips have far bigger margins than most Apple chips, Apple will get outbid by companies like Nvidia, AMD, and Broadcom. Nvidia already became TSMC's biggest customer last year. Every TSMC advanced node from N5 to N2 is fully booked and running at max capacity. It's not really realistic to make Mac, Watch,…
Panther Lake does not have great raw performance, because for now Intel has not succeeded to obtain in their new 18A CMOS process clock frequencies as high as they get in the older TSMC 3-nm process used for their previous Arrow Lake H CPU generation and the CPU cores of Panther Lake have only minor changes that can affect performance in comparison with Arrow Lake/Lunar Lake.
On the other hand, from the published reviews that I have seen, Panther Lake has significantly better performance per watt than Arrow Lake H, which can be attributed only to the Intel 18A process when compared with the TSMC 3 nm process.
The energy efficiency i.e. performance per watt ratio of CPUs is mainly determined by the fabrication process and not by the CPU design, as long as the CPU designers are competent enough (unlike the single-thread performance, which is determined mainly by the CPU design).
So there is no doubt that Apple CPUs made with the Intel 18A process will have better performance per watt than those made with a TSMC 3-nm process. Moreover, because Apple CPUs can reach a given level of performance at lower clock frequencies, they should be much less affected by the lower clock frequencies attainable with Intel 18A than the Intel CPUs.
We also do not know whether Apple intends to use the Intel 18A process (currently used for Panther Lake laptop CPUs and Clearwater Forest server CPUs), or only its successor, Intel 14A.
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The biggest reason to do this is because TSMC's N2 node and future nodes will be dominated by AI chips. Since AI chips have far bigger margins than most Apple chips, Apple will get outbid by companies like Nvidia, AMD, and Broadcom. Nvidia already became TSMC's biggest customer last year. Every TSMC advanced node from N5 to N2 is fully booked and running at max capacity. It's not really realistic to make Mac, Watch,…
I do not know on what data you base your sentence "Intel's own Panther Lake CPU tile is on 18A and it's extremely disappointing in terms of perf/watt and raw perf." Panther Lake does not have great raw performance, because for now Intel has not succeeded to obtain in their new 18A CMOS process clock frequencies as high as they get in the older TSMC 3-nm process used for their previous Arrow Lake H CPU generation and…
The most important one for efficiency is ST perf/watt. MT perf/watt is largely based on how many cores there are. You can achieve better MT perf/watt simply by having more cores (more transistors) and run them at lower clocks. Panther Lake also has an entirely new MT config with 3 tiers of cores vs 2 for Arrow Lake.
For ST perf/watt, it loses to LNL.
Keep in mind that LNL and Arrow Lake used N3B, and future N3 nodes have been much more efficient. Panther Lake CPU is also a new design which should have improved perf/watt automatically regardless of node.
Based on this, one can deduce that Intel 18A is likely a bit worse than N3B and perhaps equivalent to N4P. Keep in mind that N3B went into production in late 2022 and N4P was a 2021 node.
-dystopian
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From the article you linked: > With the new Panther Lake mobile processors, Intel has managed to successfully combine the two previous generations, Arrow Lake and Lunar Lake, as the performance is even better than with Arrow Lake, while efficiency has been improved at the same time. Even with low power limits, the performance is very competitive, and Intel (in conjunction with the new GPUs) is therefore the better ch…
Notice how it doesn't say it's more efficient than Lunar Lake. Their benchmarks say LNL is more efficient.
LNL has a much lower power consumption in the memory interface, like the Apple CPUs, which has nothing to do with the fabrication process. Also LNL is a lower performance CPU, for which it is normal to have better energy efficiency.
Only the comparison between Panther Lake and Arrow Lake H, which have equivalent structures, can be used to compare the Intel 18A and the TSMC 3-nm fabrication processes.
This comparison shows that Intel 18A ensures a better performance per watt, i.e. energy efficiency, which leads to a better multithreaded performance, but the TSMC 3-nm process, at least for now, allows higher maximum clock frequencies, which make possible a higher single-thread performance.
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Intel just bought a ton of ASML's most advanced machines (way more than TSMC) so theoretically they should be able to manufacture stuff on an equivalent node or better. And given the kind of performance and battery life we have seen from their latest chips they definitely seem to be back in the game
Do you have a source of how many total EUV machines Intel bought and TSMC bought in the last 1-2 years? Yes, Intel made the first purchase for High NA EUV machines. That's largely because they were so far behind TSMC, they took a big risk as the first adopter for High NA EUV with their upcoming 14A node to try to catch up. TSMC thinks it can keep using low NA EUV machines for N2 and A14 nodes even if they have to inc…
Intel thought they could skip buying into EUV at all and just increase their patterning steps.
That didn't work out as well as they hoped.
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Panther Lake's efficiency doesn't match M5, but it seems to be very good by all accounts. "Extremely disappointing" is a misrepresentation.
Scroll to the "Cinebench 2024 Single Power Efficiency" section.[0] It doesn't even beat Lunar Lake in efficiency (made on TSMC N3B) released in 2024. [0] https://www.notebookcheck.net/Intel-Panther-Lake-Core-Ultra-...
Both the absolute performance and the performance per watt in single-thread benchmarks are determined mainly by the CPU design and they are only slightly constrained by the CPU fabrication process.
Only the multithreaded benchmarks are useful for comparing CMOS fabrication processes, because the performance in multithreaded benchmarks (with a given cooling system) is limited mainly by the energy required to switch a logic gate, which is a characteristic of the fabrication process, and they are only weakly dependent on the CPU design, as long as the CPU design does not have obvious mistakes.
In multithreaded benchmarks, CPUs work at a fixed power consumption, determined by the maximum allowable temperature and the cooling system. A fixed power means a fixed number of gates that switch per second. The completion of a given benchmark requires a similar number of gate switchings in well designed CPUs, in which case the performance in such a benchmark is fully determined by the fabrication process. Deviations from proportionality appear when some CPUs need much less gate switchings than others to complete some work, which happens for example when a CPU has wider vector or matrix execution units, e.g. by supporting AVX-512 or SME or AMX.