I haven't had time to see the whole thing yet, but I'm quite surprised this yielded good results. If this works I would have expected CPU implementations to do some optimization around this by default given the memory latency bottleneck of the last 1.5 decades. What am I missing here?
DRAM has a design flaw from 1966. I bypassed it [video]
31–40 of 174 posts
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#32This is very much worth watching. It is a tour de force. Laurie does an amazing job of reimagining Google's strange job optimisation technique (for jobs running on hard disk storage) that uses 2 CPUs to do the same job. The technique simply takes the result of the machine that finishes it first, discarding the slower job's results... It seems expensive in resources, but it works and allows high priority tasks to run…
Update: found the bypass via the youtube blurb: https://github.com/LaurieWired/tailslayer
"Tailslayer is a C++ library that reduces tail latency in RAM reads caused by DRAM refresh stalls.
"It replicates data across multiple, independent DRAM channels with uncorrelated refresh schedules, using (undocumented!) channel scrambling offsets that works on AMD, Intel, and Graviton. Once the request comes in, Tailslayer issues hedged reads across all replicas, allowing the work to be performed on whichever result responds first."
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#33Earlier quoted context omitted.
>> It replicates data across multiple, independent DRAM channels with uncorrelated refresh schedules This is the sort of thing which was done before in a world where there was NUMA, but that is easy. Just task-set and mbind your way around it to keep your copies in both places. The crazy part of what she's done is how to determine that the two copies don't get get hit by refresh cycles at the same time. Particularly…
She determines that by having three copies. Or four. Or eight. Tis just probabilities and unlikelihood of hitting a refresh cycle across that many memory channels all at once.
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#34Re: DRAM has a design flaw from 1966. I bypassed it [video]
#35This is very much worth watching. It is a tour de force. Laurie does an amazing job of reimagining Google's strange job optimisation technique (for jobs running on hard disk storage) that uses 2 CPUs to do the same job. The technique simply takes the result of the machine that finishes it first, discarding the slower job's results... It seems expensive in resources, but it works and allows high priority tasks to run…
This is a 54 minute video. I watched about 3 minutes and it seemed like some potentially interesting info wrapped in useless visuals. I thought about downloading and reading the transcript (that's faster than watching videos), but it seems to me that it's another video that would be much better as a blog post. Could someone summarize in a sentence or two? Yes we know about the refresh interval. What is the bypass? Up…
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#36This is very much worth watching. It is a tour de force. Laurie does an amazing job of reimagining Google's strange job optimisation technique (for jobs running on hard disk storage) that uses 2 CPUs to do the same job. The technique simply takes the result of the machine that finishes it first, discarding the slower job's results... It seems expensive in resources, but it works and allows high priority tasks to run…
Can you give more context on this? Opus couldn't figure out a reference for it
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#37Love the format, and super cool to see a benchmark that so clearly shows DRAM refresh stalls, especially avoiding them via reverse engineering the channel layout! Ran it on my 9950X3D machine with dual-channel DDR5 and saw clear spikes from 70ns to 330ns every 15us or so. The hedging technique is a cool demo too, but I’m not sure it’s practical. At a high level it’s a bit contradictory; trying to reduce the tail late…
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#38She could probably have been stinking rich on this work alone, but instead she just put it up on Github. Kudos to Laurie.
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#39This is very much worth watching. It is a tour de force. Laurie does an amazing job of reimagining Google's strange job optimisation technique (for jobs running on hard disk storage) that uses 2 CPUs to do the same job. The technique simply takes the result of the machine that finishes it first, discarding the slower job's results... It seems expensive in resources, but it works and allows high priority tasks to run…
> Google's strange job optimisation technique (for jobs running on hard disk storage) Can you give more context on this? Opus couldn't figure out a reference for it
Re: DRAM has a design flaw from 1966. I bypassed it [video]
#40Earlier quoted context omitted.
> Google's strange job optimisation technique (for jobs running on hard disk storage) Can you give more context on this? Opus couldn't figure out a reference for it
This is a quite old technique. The idea, as I understood it, was that lots of data at Google was stored in triplicate for reliability purposes. Instead of fetching one, you fetched all three and then took the one that arrived first. Then you sent UDP packets cancelling the other two. For something like search where you're issuing hundreds of requests that have to resolve in a few hundred milliseconds, this substantia…