Earlier quoted context omitted.
The 99xx chips have two CPU dies, and one cache die is on each CPU die.
The 3D V-Cache sits underneath only one of the CCDs. See https://en.wikipedia.org/wiki/Ryzen#Ryzen_9000 .
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AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
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Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#22Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#23Breakdown of the (semi-clickbait) 208MB cache: 16MB L2 (8MB per die?) + 32MB L3 * 2 dies + 64MB L3 Stacked 3D V-cache * 2 For comparison, 9950X3D have a total cache of 144MB.
> 16MB L2 (8MB per die?)
It is indeed 8MB per compute die but really 1MB per core. Not shared among the entire CCD.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#24Crazy to think that my first personal computer's entire storage (was 160MB IIRC?) could fit into the L3 of a single consumer CPU! It's probably not possible architecturally, but it would be amusing to see an entire early 90's OS running entirely in the CPU's cache.
https://github.com/coreboot/coreboot/blob/main/src/soc/intel...
Context: Early in the firmware boot process the memory controller isn't configured yet so the firmware uses the cache as RAM. In this mode cache lines are never evicted since there's no memory to evict them to.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#25Probably fun for those who already bought DDR5 memory... still kicking myself for not just pulling the trigger on that 128GB dual stick kit I looked at for $600 back in September. Now it's listed at $4k...
Meanwhile I hope my AM4 will chug along a few more years.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#26Given that the dies still have L3 on them does this count as L4 or does the hardware treat it as a single pool of L3?
Would be neat to have an additional cache layer of ~1 GB of HBM on the package but I guess there's no way that happens in the consumer space any time soon.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#27Earlier quoted context omitted.
The 99xx chips have two CPU dies, and one cache die is on each CPU die.
The 3D V-Cache sits underneath only one of the CCDs. See https://en.wikipedia.org/wiki/Ryzen#Ryzen_9000 .
That's what's different about this one. "Enter the Ryzen 9 9950X3D2 Dual Edition, a mouthful of a chip that includes 64MB of 3D V-Cache on both processor dies, without the hybrid arrangement that has defined the other chips up until now."
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#28Crazy to think that my first personal computer's entire storage (was 160MB IIRC?) could fit into the L3 of a single consumer CPU! It's probably not possible architecturally, but it would be amusing to see an entire early 90's OS running entirely in the CPU's cache.
Maybe in 50 years the cache of CPUs and GPUs will be 1TB. Enough to run multiple LLMs (a model entirely run for each task). Having robots like in the movies would need LLMs much much faster than what we see today.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#29The extra cache doesn't do a damn thing (maybe +2%)
The lower leakage currents at lower voltages allowed them to implement a far more aggressive clock curve from the factory. That's where the higher allcore clock comes from (+30W TDP)
I'm not complaining at all, I think this is an excellent way to leverage binning to sell leftover cache.
Though if I may complain, Ars used to actually write about such things in their articles instead of speculate in a way that suspiciously resembles what an AI would write.
Re: AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
#309950X3D2? AMD, who is making you name your products like this? At some point just give up and name the chip a UUID already.