Earlier quoted context omitted.
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
I'd want to know why they had such a system as a single point of failure
Designing a Low Latency 10G Ethernet Core (2023)
21–30 of 83 posts
Re: Designing a Low Latency 10G Ethernet Core (2023)
#22less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#23It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
Re: Designing a Low Latency 10G Ethernet Core (2023)
#24Earlier quoted context omitted.
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
why do you assume the full ethernet header? IIRC. cut-through only needs the first 6 bytes. Since it only needs the destination address for the port lookup. Potentially the first bit, on broadcast.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#25Earlier quoted context omitted.
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
The way to think is the opposite: your system is making millions per hour.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#26Earlier quoted context omitted.
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
I'd want to know why they had such a system as a single point of failure
Re: Designing a Low Latency 10G Ethernet Core (2023)
#27Earlier quoted context omitted.
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
The way to think is the opposite: your system is making millions per hour.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#28Re: Designing a Low Latency 10G Ethernet Core (2023)
#29Earlier quoted context omitted.
The way to think is the opposite: your system is making millions per hour.
What about when something goes wrong because you overlooked some detail?
Re: Designing a Low Latency 10G Ethernet Core (2023)
#30less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Essentially a few ns after the header is received it will already be passed on to the output port after some signal conditioning, which happens almost without latency. A typical 'high speed' switch will have 800 ns round trip, so that 60 ns quoted here is actually quite impressive.