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486Tang – 486 on a credit-card-sized FPGA board

nand2mario.github.io

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Re: 486Tang – 486 on a credit-card-sized FPGA board

#21
I would love to see ancient tech fabbed out on modern processes.

What's the smallest SOC you could design to run DOOM? What power envelope would that consume (exclusing display/speakers/etc.) At that size and (optimized) transistor count, what speeds could we realistically achieve?

What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like?

Every time I see a project like this, these thoughts run through my head.

Re: 486Tang – 486 on a credit-card-sized FPGA board

#22
post #7

> Obviously, at the time of the 80486, DDR didn’t exist, so SDRAM is a natural fit. Neither are a fit, SDRAM was a Pentium/K-6 standard (PC66); the DIMMs ran faster than a non-OC'ed 486 bus, which ran at half the clock of the CPU. 486 "natural fit" would be FPM or EDO, if you wanted to be era-correct. There were probably some off the wall 486 motherboards back then that supported SDR (post-1993...), but those would h…

Author here. You’re right—EDO or FPM would be correct for the era. But as others have noted, DDR3 is fundamentally different from early 1990s memory, and it simply won’t run at the very low clock speeds of a 486. SDRAM, on the other hand, behaves in a way that’s much more comparable to the memory used back then.

Re: 486Tang – 486 on a credit-card-sized FPGA board

#23

Doesn’t DDR just stand for Double-Data-Rate? So you implemented basic DDR on top is sdram. Not a bad approach, just wanted to point it out.

It does, yes. But the DDR RAM available on the target board is DDR3 which is actually quite inconvenient for retro projects for a number of reasons. Quite apart from the increased complexity, the most important difference is that there's a minimum speed as well as a maximum speed for modern DDR RAM, which means there's usually quite a narrow window of achievable clock rates when getting an FPGA to talk to DDR3. I sus…

Yes, for exactly the reason. SDRAM is much easier to work with in retro computing than DDR.

Re: 486Tang – 486 on a credit-card-sized FPGA board

#24

Earlier quoted context omitted.

It does, yes. But the DDR RAM available on the target board is DDR3 which is actually quite inconvenient for retro projects for a number of reasons. Quite apart from the increased complexity, the most important difference is that there's a minimum speed as well as a maximum speed for modern DDR RAM, which means there's usually quite a narrow window of achievable clock rates when getting an FPGA to talk to DDR3. I sus…

Yes, for exactly the reason. SDRAM is much easier to work with in retro computing than DDR.

My first DDR system, an Athlon XP, feels like a very different beast than my 440BX with SDRAM despite being only a couple years newer. :)

Re: 486Tang – 486 on a credit-card-sized FPGA board

#25
post #19
post #4

I miss Intel's Quark chips. Tiny, cheap, and Pentium enough.

Didn't they have the F00F bug? (Thanks, I keep misremembering) How much more Pentium do you want?

I believe the F00F bug was patched out pretty quickly in the Pentium's B2 stepping. Nevertheless, some OSs still have mitigations if they detect an affected CPU (e.g. OpenBSD).

Re: 486Tang – 486 on a credit-card-sized FPGA board

#28
post #25
post #19

Earlier quoted context omitted.

Didn't they have the F00F bug? (Thanks, I keep misremembering) How much more Pentium do you want?

I believe the F00F bug was patched out pretty quickly in the Pentium's B2 stepping. Nevertheless, some OSs still have mitigations if they detect an affected CPU (e.g. OpenBSD).

It wasn’t even discovered until 1997, so no that wasn’t exactly early in the Pentium lifecycle at all. There were multiple models and millions of devices affected.

Re: 486Tang – 486 on a credit-card-sized FPGA board

#29

I would love to see ancient tech fabbed out on modern processes. What's the smallest SOC you could design to run DOOM? What power envelope would that consume (exclusing display/speakers/etc.) At that size and (optimized) transistor count, what speeds could we realistically achieve? What would a massively-multicore (gpu-style with multi-hundreds or more of cores) one of these run like? Every time I see a project like…

That is a cool idea for sure. It's fun to imagine where the original x86 platform ({80,2,3,4}86) would have gone if it hadn't been remade with the Pentium (superscaler).
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