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Earlier quoted context omitted.
> Did the LLM actually do the routing? Good question. KiCAD once had a router, built in, or sort of built in, but it was taken out for licensing reasons. So who's doing that?
freerouting plugin is available as a standalone program. It's pretty good. You export DSN from kicad and use freerouting. Not as simple as button click though.
So what did this project use?
The blog post isn’t clear: Did the LLM actually do the routing? The only screenshot showing connected traces comes after the author says they added ground fills and “tidied up the layout” It’s amazing that this worked at all, but to be clear this layout is actually very bad. Just look at that minimum width trace used to carry power across the entire board and into the ESP32. Using min width traces and wrapping them a…
The video seems more clear. The LLM generated the BOM and netlist using atopile, a tool for specifying the equivalent of a schematic in code. He did the placement and routing in KiCad in the usual way, presumably by hand. ETA: Other commenters suspect a traditional autorouter based on the poor layout quality. I agree that's also possible, and nothing in the video excludes that. It definitely wasn't the LLM, though.
I assumed the author was more experienced, I suppose this is more of an entry level hobbyist blog. There are some very fundamental problems with routing PCBs like this that are covered in introductory materials.
Earlier quoted context omitted.
freerouting plugin is available as a standalone program. It's pretty good. You export DSN from kicad and use freerouting. Not as simple as button click though.
Freerouting used to be more closely integrated with KiCAD. So what did this project use?
The blog post isn’t clear: Did the LLM actually do the routing? The only screenshot showing connected traces comes after the author says they added ground fills and “tidied up the layout” It’s amazing that this worked at all, but to be clear this layout is actually very bad. Just look at that minimum width trace used to carry power across the entire board and into the ESP32. Using min width traces and wrapping them a…
Also, it certainly wasn't the LLM; atopile doesn't allow you to specify routing as far as I'm aware, their docs seem to tell you to route in KiCad.
Except that:
- no parts placement
- no routing
Frameworks like atopile, tscircuit (disclaimer: I’m a tscircuit lead maintainer) and JITX are critical here because they enable the LLM to output the deep knowledge it already has. The author is missing a couple pieces to really get great output: 1) Context-friendly datasheets 2) DRC/Semantic review 3) LLM-compatible layout methods
The hardest to build is (3) and what I spend 90% of my time on. AI knows how do do spatial layout for things like flex or css grid but doesn’t have a layout method for PCBs. Our approach w/ tscircuit is to develop new layout systems that either match templates, new heuristic layouts (we are developing one called “pack”), or solve simple spatial constraints.
But tldr; it is only a matter of time before AI can output PCBs. It is not simple but we know what works with LLMs from witnessing the evolution of AI for website generation
Can’t wait for cheap vibe coded electronics to flood Amazon and burn houses down.
While I think that AI tools can be quite useful for coding, PCB design, and other tasks like that, the setup of this experiment makes it really hard for the LLM to fail. The author's prompt is basically already a meticulous specification of the PCB, even proactively telling the LLM to avoid certain pitfalls ("GPIO19 and GPIO20 on the ESP32-S3 module are USB D- and D+ respectively. Make sure these nets are labeled cor…
The blog post isn’t clear: Did the LLM actually do the routing? The only screenshot showing connected traces comes after the author says they added ground fills and “tidied up the layout” It’s amazing that this worked at all, but to be clear this layout is actually very bad. Just look at that minimum width trace used to carry power across the entire board and into the ESP32. Using min width traces and wrapping them a…
Is it really so implausible that these constraints could be built into the process/algorithm/agentic workflow?