Optimizing Matrix Multiplication on RDNA3
seb-v.github.io
Optimizing Matrix Multiplication on RDNA3
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Re: Optimizing Matrix Multiplication on RDNA3
#2Re: Optimizing Matrix Multiplication on RDNA3
#3Well done!
Re: Optimizing Matrix Multiplication on RDNA3
#4this is overblown at least wrt forward compatibility - all of the instructions used are in RDNA4 and most of them are even in CDNA3 (CDNA4 isn't public yet?) and the ones that aren't exactly there are only slightly renamed (ds_load -> ds_read). Sure it's annoying but it's not the end of the world to have some `#ifdef`s in your code (that's not very much different from what the compiler itself is going to do anyway).
Re: Optimizing Matrix Multiplication on RDNA3
#5Re: Optimizing Matrix Multiplication on RDNA3
#6This is really cool. 60% is no joke and as a 7900XTX owner I would love the performance boost. Well done!
Re: Optimizing Matrix Multiplication on RDNA3
#7Re: Optimizing Matrix Multiplication on RDNA3
#8Is the author a genius or has AMD questionable software?
It's probably not surprising that you can grind a decent improvement over a general solution, and many of the improvements shown here will need to be re-balanced, or even simply not work, for kernels working on different matrix layouts. Similarly for trying to work on different hardware - even in the same architecture and generation these sort of details are often changing.
And all that required going down to the ISA level, which is a lot less easy (certainly less documented) for Nvidia - for example the "inspiration" post linked [0] on CUDA didn't beat cuBLAS also didn't try modifying the SASS directly, so there might be similar level gains unrealized there.
Re: Optimizing Matrix Multiplication on RDNA3
#9Is the author a genius or has AMD questionable software?
Many of the optimizations here rely heavily on the size of matrix and it's relationship to hardware specific details, like LDS size, how they're banked and register count. It's probably not surprising that you can grind a decent improvement over a general solution, and many of the improvements shown here will need to be re-balanced, or even simply not work, for kernels working on different matrix layouts. Similarly f…
but you're acting like they pick these numbers using a random number generator for each generation when it's just reasonable/rational stuff like "here's 2x more LDS or more registers for free because the new process node is 2x smaller". like you must realize that they're not throwing everything away and starting completely from scratch for every new gen right? incidentally, while LDS will grow and # of registers will grow, there's absolutely no way they'd change the banking - e.g., CUDA hasn't changed it since 2.0.
Re: Optimizing Matrix Multiplication on RDNA3
#10Earlier quoted context omitted.
Many of the optimizations here rely heavily on the size of matrix and it's relationship to hardware specific details, like LDS size, how they're banked and register count. It's probably not surprising that you can grind a decent improvement over a general solution, and many of the improvements shown here will need to be re-balanced, or even simply not work, for kernels working on different matrix layouts. Similarly f…
> like LDS size, how they're banked and register count. but you're acting like they pick these numbers using a random number generator for each generation when it's just reasonable/rational stuff like "here's 2x more LDS or more registers for free because the new process node is 2x smaller". like you must realize that they're not throwing everything away and starting completely from scratch for every new gen right? i…
I'm not trying to minimize the work here, it's interesting and a good example of the sort of lengths you can go to in order to squeeze that last little bit of performance out (and again, showing the advantages of public ISA documentation and support for users working at that level), I just took issue to the parent comment seeming to use this work as evidence of a poor baseline.