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Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).
Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).
[1]:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
Earlier quoted context omitted.
Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).
According to this [1] wikipedia article, the only feature Sapphire Rapids doesn't support is VP2INTERSECT. [1]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
https://arxiv.org/abs/2112.06342
https://www.reddit.com/r/asm/comments/110pld0/fasterthannati...
Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
Earlier quoted context omitted.
According to this [1] wikipedia article, the only feature Sapphire Rapids doesn't support is VP2INTERSECT. [1]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
It seems that there are faster alternatives to it https://arxiv.org/abs/2112.06342 https://www.reddit.com/r/asm/comments/110pld0/fasterthannati...
Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it.
Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who ever could have taken advantage of it and benefitted from it. For general purpose workloads, having the E cores enabled (and therefore AVX-512 disabled) was faster. You had to have an extremely specific workload that didn't scale well with additional cores and also had hot loops that benefitted from AVX-512, which was not very common.
So you're right: They never wanted people to use it. It wasn't advertised and wasn't usable without sacrificing all of the E cores and doing a lot of manual configuration work. I suspect they didn't want people using it because they never validated it. AVX-512 mode increased the voltages, which would impact things like failure rate and warranty returns. They probably meant to turn it off but forgot in the first versions.
Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
Earlier quoted context omitted.
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who e…
Spoiler if you don’t want to read through the (wonder but many) paragraphs of exposition: the instruction is `vp2intersectq k, zmm, zmm`.
Also, the fact that it's deprecated by Intel.