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Simple CPU Design

simplecpudesign.com

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Re: Simple CPU Design

#31

Post by spencerflem »

linguistbreaker wrote: post #30
spencerflem wrote: post #27

Earlier quoted context omitted.

I believe that it does, I'm worried long term that it will discourage people from making and curating webpages themselves though.

Definitely a possibility - hopefully AI will similarly empower creation of better content instead of AI slop noise. In fact I wonder if Claude.ai could come up with similar CPU teaching tools and a syllabus based on some of the great resources linked in this discussion.

I mean, probably, but only because it was trained on this already.

For new things though, why would you bother posting them to the internet if you can't use it to build an audience or make a connection.

Re: Simple CPU Design

#32

Post by linguistbreaker »

spencerflem wrote: post #31
linguistbreaker wrote: post #30

Earlier quoted context omitted.

Definitely a possibility - hopefully AI will similarly empower creation of better content instead of AI slop noise. In fact I wonder if Claude.ai could come up with similar CPU teaching tools and a syllabus based on some of the great resources linked in this discussion.

I mean, probably, but only because it was trained on this already. For new things though, why would you bother posting them to the internet if you can't use it to build an audience or make a connection.

and possibly not even credited for the content you created...

True

Re: Simple CPU Design

#33

Post by mhh__ »

recursivedoubts wrote: post #3

I teach the introduction to computing class at MSU and agree entirely: most students need to start with the absolutely most simple introduction to computing possible. My favorite two models are: The Scott CPU https://www.youtube.com/watch?v=cNN_tTXABUA (great book, website is now offline unfortunately: https://web.archive.org/web/20240430093449/https://www.butho... ) An extremely simple non-pipelined 8 bit CPU. The e…

My first introduction to this stuff was also the little man computer. I won't say when as it might make some readers feel old, but very fond memories of playing around with it.

Similarly fond memories of the teacher letting me just do my own thing at the back of the classroom after noticing I was writing an interpreter rather than hard-coding all the logic in the task.

Probably hard to state just how good of an introduction he was to programming, actually. Not a codeforces-style geek but was constantly drilling the value of writing beautiful code that is as simple as possible to a bunch of 14 year olds of which probably only me and a friend were listening. Maybe it's not coincidence that amongst my friends/mutuals from that age there are core maintainers for I think three for pretty big languages

Re: Simple CPU Design

#35

Post by allenrb »

ranger207 wrote: post #21
nxobject wrote: post #17

As much as I really benefited from being able to internalize system architectures like these many times over… I do wish now, as someone who ended up in software, that there were similar hand-holdy third guides to implementing the “core” of out-of-order superscalar execution engines, too. They’re crucial to understanding how modern processors _kinda actually work to a zeroth order approximation_, even though it’s impo…

At Georgia Tech I had one class (CS 2110) that dealt with implementing a simple in-order non-pipelined processor, one class that dealt with implementing a pipelined processor (CS 2210), then two classes (CS 4290 and CS 3220 IIRC) that dealt with implementing an out-of-order processor (4290 was more theory and also covered caches; 3220 was entirely implementing it on an FPGA). So, that sort of thing does exist, but ID…

That sounds like a great sequence! Offhand, I don’t think there were any OOO microprocessors when I did computer architecture at Tech (Go Jackets!)

Re: Simple CPU Design

#36

Post by wyager »

For anyone interested in a "not-so-simple" CPU design, I have a couple old college assignments from a CPU design class that may be fun to peruse:

This one is a 4-stage pipelined CPU: https://github.com/wyager/Lambda16

This one is a superscalar out-of-order CPU: https://github.com/wyager/Lambda17

Both are written in Clash, which is a subset of Haskell that compiles to target FPGAs. It's an incredibly OP HDL.

I don't think I ever ran the second one on an actual FPGA, because at the time values of type `Char` wouldn't synthesize, but I think the Clash compiler fixed that at some point.

Re: Simple CPU Design

#38

Post by hnuser123456 »

recursivedoubts wrote: post #3

I teach the introduction to computing class at MSU and agree entirely: most students need to start with the absolutely most simple introduction to computing possible. My favorite two models are: The Scott CPU https://www.youtube.com/watch?v=cNN_tTXABUA (great book, website is now offline unfortunately: https://web.archive.org/web/20240430093449/https://www.butho... ) An extremely simple non-pipelined 8 bit CPU. The e…

Which MSU?

Re: Simple CPU Design

#39

Post by phendrenad2 »

cjfd wrote: post #9

I considered trying to do a simple CPU design from logic gates too. But I ended up wondering about some of the performance characteristics. Maybe some people who are knowledgeable are reading this. What I am wondering about is the switching speed of logic gates as compared to the signal speed in the electric connections for a realistic CPU. I.e., how many logic gate lengths (assume logic gates to be square) does an e…

The performance characteristics won't be great, but it would still be a fun project. In fact one of the early 32-bit RISC processors, PA-RISC, was originally shipped as a set of four large boards covered in discrete 74-series logic. Which actually includes a large ALU chip (without which the design would probably span 8 boards instead...)

Re: Simple CPU Design

#40

Post by dreamcompiler »

timthorn wrote: post #15
cjfd wrote: post #9

I considered trying to do a simple CPU design from logic gates too. But I ended up wondering about some of the performance characteristics. Maybe some people who are knowledgeable are reading this. What I am wondering about is the switching speed of logic gates as compared to the signal speed in the electric connections for a realistic CPU. I.e., how many logic gate lengths (assume logic gates to be square) does an e…

If you want to go a step further, here's one built from discrete transistors: https://www.megaprocessor.com/

This machine is now at the Computer History Museum in Cambridge. I saw it there last year. Highly recommended.

https://www.computinghistory.org.uk/

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