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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#101

Post by ChuckMcM »

girvo wrote: post #84
ChuckMcM wrote: post #2

I think this is an important step, but it skips over that 'fault tolerant routing architecture' means you're spending die space on routes vs transistors. This is exactly analogous to using bits in your storage for error correcting vs storing data. That said, I think they do a great job of exploiting this technique to create a "larger"[1] chip. And like storage it benefits from every core is the same and you don't nee…

> Xilinx was still aggressively suing people who put SERDES ports on FPGAs This so isn't important to your overall point, but where would I begin to look into this? Sounds fascinating!

Well this was the patent they were threatening with as I recall (https://patents.google.com/patent/US20030023912A1/en) and there was this one too: https://patents.google.com/patent/US5576554A/en

Basically the "secret sauce" of the startup recruiting me was that they were going to do wafer scale FPGAs that could be tiled together to build arbitrarily complex systems like military phased array radars and such. All very hush hush but apparently they had recruited some key talent from Xilinx which was annoying Xilinx.

Re: 100x defect tolerance: How we solved the yield problem

#102

Post by ChuckMcM »

bigdict wrote: post #100
ChuckMcM wrote: post #89

Earlier quoted context omitted.

I would guess you're not asking a serious question here but if you were feel free to contact me, it's why I put my email address in my profile.

Why are you assuming bad faith?

What gave you the impression I was assuming bad faith? It's off topic to the discussion (which is fine) but can be annoying in the middle of an HN thread.

Re: 100x defect tolerance: How we solved the yield problem

#103

Post by Dylan16807 »

ryao wrote: post #54
sroussey wrote: post #15

Earlier quoted context omitted.

I wonder if you could… just not cut the wafer at all??

I suspect this would cause alignment issues since you could literally rotate it into the wrong position when doing soldering. That said, perhaps they could get away with cutting less and using more.

If you want to have nice straight edges to clamp into place, then you only need to shave off four slivers. You can lose a couple percent instead of more than a third.

Re: 100x defect tolerance: How we solved the yield problem

#104

Post by __Joker »

ChuckMcM wrote: post #89
__Joker wrote: post #75

Earlier quoted context omitted.

"While I continue to believe that many people are going to collectively lose trillions of dollars ultimately pursuing "AI" at this stage" Can you please explain more why you think so ? Thank you.

I would guess you're not asking a serious question here but if you were feel free to contact me, it's why I put my email address in my profile.

Really sorry, if the question came as snarky or if otherwise. Those were not my intent.

Related to AI given all around noise, really wanted to understand kind of contrarian view of monetary aspects.

Once again, apologies if the question seems frivolous.

Re: 100x defect tolerance: How we solved the yield problem

#105

Post by Dylan16807 »

twic wrote: post #87
Paul_Clayton wrote: post #74

Earlier quoted context omitted.

The enthalpy of vaporization of water (at standard pressure) is listed by Wikipedia[1] as 2.257 kJ/g, so boiling 462 grams would require an additional 1.04 MJ, adding 26 seconds. Cerebras claims a "peak sustained system power of 23kW" for the CS-3 16 Rack Unit system[2], so clearly the power density is lower than for an H100. [1] https://en.wikipedia.org/wiki/Enthalpy_of_vaporization#Other... [2] https://cerebras.ai/…

On a tangent: has anyone built an active cooling system which operates in a partial vacuum? At half atmospheric pressure, water boils at around 80 C, which i believe is roughly the operating temperature for a hard-working chip. You could pump water onto the chip, have it vapourise, taking away all that heat, then take the vapour away and condense it at the fan end. This is how heat pipes work, i believe, but heat pip…

> This is how heat pipes work, i believe, but heat pipes aren't pumped, they rely entirely on heat-driven flow. I would have thought there were pumped heat pipes.

Do you have a particular benefit in mind that a pump would help with?

Re: 100x defect tolerance: How we solved the yield problem

#106

Post by anon373839 »

KronisLV wrote: post #98
mschuster91 wrote: post #81

Earlier quoted context omitted.

It's a hype cycle with many of the hypers and deciders having zero idea about what AI actually is and how it works. ChatGPT, while amazing, is at its core a token predictor, it cannot ever get to an AGI level that you'd assume to be competitive to a human, even most animals. And just as every other hype cycle, this one will crash down hard. The crypto crashes were bad enough but at least gamers got some very cheap GP…

> And just as every other hype cycle, this one will crash down hard. Isn't that an inherent problem with pretty much everything nowadays: crypto, blockchain, AI, even the likes of serverless and Kubernetes, or cloud and microservices in general. There's always some hype cycle where the people who are early benefit and a lot of people chasing the hype later lose when the reality of the actual limitations and the real…

> I don't think the current "AI" is special in any way

As someone who loves to pour ice water on AI hype, I have to say: you can't be serious.

The current AI tech has opened up paths to develop applications that were impossible just a few years ago. Even if the tech freezes in place, I think it will yield substantial economic value in the coming years.

It's very different from crypto, the main use case for which appears to be money laundering.

Re: 100x defect tolerance: How we solved the yield problem

#108

Post by bigdict »

ChuckMcM wrote: post #102
bigdict wrote: post #100

Earlier quoted context omitted.

Why are you assuming bad faith?

What gave you the impression I was assuming bad faith? It's off topic to the discussion (which is fine) but can be annoying in the middle of an HN thread.

> What gave you the impression I was assuming bad faith?

You said "I would guess you're not asking a serious question here"

Re: 100x defect tolerance: How we solved the yield problem

#109

Post by CamperBob2 »

mschuster91 wrote: post #81
__Joker wrote: post #75

Earlier quoted context omitted.

"While I continue to believe that many people are going to collectively lose trillions of dollars ultimately pursuing "AI" at this stage" Can you please explain more why you think so ? Thank you.

It's a hype cycle with many of the hypers and deciders having zero idea about what AI actually is and how it works. ChatGPT, while amazing, is at its core a token predictor, it cannot ever get to an AGI level that you'd assume to be competitive to a human, even most animals. And just as every other hype cycle, this one will crash down hard. The crypto crashes were bad enough but at least gamers got some very cheap GP…

it cannot ever get to an AGI level that you'd assume to be competitive to a human, even most animals.

Suppose you turn out to be wrong. What would convince you?

Re: 100x defect tolerance: How we solved the yield problem

#110

Post by fspeech »

sfink wrote: post #79
Neywiny wrote: post #40

Understanding that there's inherent bias by them being competitors of the other companies, but still this article seems to make some stretches. If you told me you had an 8% core defect rate reduced 100x, I'd assume you got to close to 99% enablement. The table at the end shows... Otherwise. They also keep flipping between cores, SMs, dies, and maybe other block sizes. At the end of the day I'm not very impressed. The…

I think you're missing the point. The comparison is not between 93% and 92%. The comparison is between what they're getting (93%) and what you'd get if you scaled up the usual process to the core size they're using (0%). They are doing something different (namely: a ~whole wafer chip) that isn't possible without massively boosting the intra-chip redundancy. (The usual process stops working once you no longer have any…

There is nothing inherently good about wafer scale. It's actually harder to dissipate heat and enable hybrid bonding with DRAM. So the gp is entirely correct that you need to actually show higher silicon utilization to be even considered as being something worthwhile.
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