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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#21

Post by olejorgenb »

yannyu wrote: post #9
olejorgenb wrote: post #6

Earlier quoted context omitted.

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

> I assume they don't pattern the unused area, so the process should be quicker? The primary driver of time and cost in the fabrication process is the number of layers for the wafers, not the surface area, since all wafers going through a given process are the same size. So you generally want to maximize the number of devices per wafer, because a large part of your costs will be calculated at the per-wafer level, not…

Yes, but my understanding is that the wafer is exposed in multiple steps, so there would still be less exposure steps? Probably insignificant compared to all the rest though. (Etching, moving the wafer, etc.)

EDIT: to clarify - I mean the exposure of one single pattern/layer is done in multiple steps. (https://en.wikipedia.org/wiki/Photolithography#Projection)

Re: 100x defect tolerance: How we solved the yield problem

#22

Post by nine_k »

wizzard0 wrote: post #3

this is an important reminder that all digital electronics is really analog but with good correction circuitry. and run-time cpu and memory error rates are always nonzero too, though orders of magnitude lower than chip yield rates

CPUs may be very digital inside, but DRAM and flash memory are highly analog, especially MLC flash. DDR4 even has a dedicated training mode [1], during which DRAM and the memory controller learn the quirks of particular data lines and adjust to them, in order to communicate reliably.

[1]: https://www.systemverilog.io/design/ddr4-initialization-and-...

Re: 100x defect tolerance: How we solved the yield problem

#23

Post by yannyu »

olejorgenb wrote: post #21
yannyu wrote: post #9

Earlier quoted context omitted.

> I assume they don't pattern the unused area, so the process should be quicker? The primary driver of time and cost in the fabrication process is the number of layers for the wafers, not the surface area, since all wafers going through a given process are the same size. So you generally want to maximize the number of devices per wafer, because a large part of your costs will be calculated at the per-wafer level, not…

Yes, but my understanding is that the wafer is exposed in multiple steps, so there would still be less exposure steps? Probably insignificant compared to all the rest though. (Etching, moving the wafer, etc.) EDIT: to clarify - I mean the exposure of one single pattern/layer is done in multiple steps. ( https://en.wikipedia.org/wiki/Photolithography#Projection )

The number of exposure steps would be unrelated to the (surface area) size of die/device that you're making. In fact, in semiconductor manufacturing you're typically trying to maximize the number of devices per wafer because it costs the same to manufacture 1 device with 10 layers vs 100 devices with 10 layers on the same wafer. This goes so far as to have companies or business units share wafers for prototyping runs so as to minimize cost per device (by maximizing output per wafer).

Also, etching, moving, etc is all done on the entire wafer at the same time generally, via masks and baths. It's less of a pencil/stylus process, and more of a t-shirt silk-screening process.

Re: 100x defect tolerance: How we solved the yield problem

#24

Post by mattashii »

yannyu wrote: post #9
olejorgenb wrote: post #6

Earlier quoted context omitted.

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

> I assume they don't pattern the unused area, so the process should be quicker? The primary driver of time and cost in the fabrication process is the number of layers for the wafers, not the surface area, since all wafers going through a given process are the same size. So you generally want to maximize the number of devices per wafer, because a large part of your costs will be calculated at the per-wafer level, not…

Yes, but isn't a big driver of layer costs the cost of the machines to build those layers?

For patterning, a single iteration could be (example values, no actual values used, probably only ballpark accuracy) on a 300M$ EUV machine with 5-year write off cycle, patterns on average 180 full wafers /hour. Excluding energy usage and service time, each wafer that needs full patterning would cost ~38$. If each wafer only needed half the area patterned, the lithography machine might only spend half its usual time on such a wafer, and that could double the throughput of the EUV machine, halving the write-off based cost component of such a patterning step.

Given that each layer generally consists of multiple patterning steps, a 10-20% reduction in those steps could give a meaningful reduction in time spent in the machines whose time spend on the wafer depends on the used wafer area.

This of course doesn't help reduce time in polishing or etching (and other steps that happen with whole wafers at a time), so it won't be as straightforward as % reduction in wafer area usage == % reduction in cost, but I wouldn't be surprised if it was a meaningful percentage.

Re: 100x defect tolerance: How we solved the yield problem

#25

Post by axus »

sroussey wrote: post #15
guyzero wrote: post #10

Earlier quoted context omitted.

I've never cut a wafer, but I assume cutting is hard and single straight lines are the easiest.

I wonder if you could… just not cut the wafer at all??

Might be jumping in without reading, but the chips you cut out of the wafer have to be delivered to physically different locations.

Re: 100x defect tolerance: How we solved the yield problem

#27

Post by NickHoff »

Neat. What about power density?

An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW.

That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)?

amount of water = (die area of 46225 mm^2) * (1 cm deep) * (density of water) = 462 grams

energy needed = (specific heat of water) * (80 kelvin difference) * (462 grams) = 154 kJ

time = 154 kJ / 39.8 kW = 3.9 seconds

This thing will boil (!) a centimeter of water in 4 seconds. A typical consumer water cooler radiator would reduce the temperature of the coolant water by only 10-15 C relative to ambient, and wouldn't like it (I presume) if you pass in boiling water. To use water cooling you'd need some extreme flow rate and a big rack of radiators, right? I don't really know. I'm not even sure if that would work. How do you cool a chip at this power density?

Re: 100x defect tolerance: How we solved the yield problem

#28

Post by georgeburdell »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

They probably pattern at least next nearest neighbors for local uniformity. That’s just litho though. The rest of the process is done all at once on the wafer
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