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100x defect tolerance: How we solved the yield problem

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Re: 100x defect tolerance: How we solved the yield problem

#11

Post by ajb »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

Good question. I think the wafer has a cost per area which is fairly significant, but I don't have any figures. There has historically been a push to utilise them more efficiently, eg by building fabs that can process larger wafers. Although mask exposure would be per processed area, I think that there are also some proportion of processing time which is per wafer, so the unprocessed area would have an opportunity cost relating to that.

Re: 100x defect tolerance: How we solved the yield problem

#12

Post by mhh__ »

IshKebab wrote: post #7

TSMC also have a manufacturing process used by Tesla's Dojo where you can cut up the chips, throw away the defective ones, and then reassemble working ones into a sort of wafer scale device (5x5 chips for Dojo). Seems like a more logical design to me.

Amazing. I clicked a button in the azure deployment menu today...

Re: 100x defect tolerance: How we solved the yield problem

#13

Post by nine_k »

ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

It's a win because they have to test one chip, and don't have to spend resources on connecting the chiplets. The latter costs a lot (though it has other advantages). I suspect that a chiplet-based device with total 900k cores would just be not viable due to the size constraints.

If their routing around the defects is automated enough (given the highly regular structure), it may be a massive economy of efforts on testing and packaging the chip.

Re: 100x defect tolerance: How we solved the yield problem

#14

Post by sroussey »

ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

It’s a win if you can use the wafer as opposed to throwing it away.

Re: 100x defect tolerance: How we solved the yield problem

#15

Post by sroussey »

guyzero wrote: post #10
Scaevolus wrote: post #8

Earlier quoted context omitted.

Why does their chip have to be rectangular, anyways? Couldn't they cut out a (blocky) circle too?

I've never cut a wafer, but I assume cutting is hard and single straight lines are the easiest.

I wonder if you could… just not cut the wafer at all??

Re: 100x defect tolerance: How we solved the yield problem

#16

Post by nine_k »

Scaevolus wrote: post #8
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Why does their chip have to be rectangular, anyways? Couldn't they cut out a (blocky) circle too?

Rather I wonder why do they even need to cut the extra space, instead of putting something there. I suppose that the structure of the device is highly rectangular from the logical PoV, so there's nothing useful to put there. I suspect smaller unrelated chips can be produced on these areas along the way.

Re: 100x defect tolerance: How we solved the yield problem

#18

Post by highfrequency »

To summarize: localize defect contamination to a very small unit size, by making the cores tiny and redundant.

Analogous to a conglomerate wrapping each business vertical in a limited liability veil so that lawsuits and bankruptcy do not bring down the whole company. The smaller the subsidiaries, the less defect contamination but also the less scope for frictionless resource and information sharing.

Re: 100x defect tolerance: How we solved the yield problem

#19

Post by yannyu »

Scaevolus wrote: post #8
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Why does their chip have to be rectangular, anyways? Couldn't they cut out a (blocky) circle too?

The cost driver for fabbing out wafers is the number of layers and the number of usable devices per wafer. Higher layer count increases cost and tends to decrease yield, and more robust designs with higher yields increase usable devices per wafer. If circles or other shapes could help with either of those, they would likely be used. Generally the end goal is to have the most usable devices per wafer, so they'll be packed as tightly as possible on the wafer so as to have the highest potential output.

Re: 100x defect tolerance: How we solved the yield problem

#20

Post by pulvinar »

olejorgenb wrote: post #6
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Is the wafer itself so expensive? I assume they don't pattern the unused area, so the process should be quicker?

There's also no reason they couldn't pattern that area with some other suitable commodity chips. Like how sawmills and butchers put all cuts to use.
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