Execution units are often pipelined
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Execution units are often pipelined
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Re: Execution units are often pipelined
#2For x86 cores this is visible in Agner Fog's instruction performance tables: https://agner.org/optimize/#manuals
The latency shows after how many cycles the result of an instruction can be consumed by another, while the throughput shows how many such instructions can be pipelined per cycle, i.e. in parallel.
Re: Execution units are often pipelined
#3Is this still the case if I have different ALU operations. Say I have a single ALU on a single x86 core. Would the ALU be able to interleave say ADD and MULs? or would I incur the latency measure for each operation switch?
I know that some ALU's have multiple ADD complexes, and I assume that would influence the answer, hence why I specified x86.
Re: Execution units are often pipelined
#4These days CPUs are so complex and have so many interdependencies that the best way to simulate them is simply to run them!
In most real code the high throughput of these sorts of operations means that something else is the limiting factor. And if multiplier throughput is limiting performance then you should be using SIMD or a GPU.
Re: Execution units are often pipelined
#5Is this still the case if I have different ALU operations. Say I have a single ALU on a single x86 core. Would the ALU be able to interleave say ADD and MULs? or would I incur the latency measure for each operation switch? I know that some ALU's have multiple ADD complexes, and I assume that would influence the answer, hence why I specified x86.
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Re: Execution units are often pipelined
#6Is this still the case if I have different ALU operations. Say I have a single ALU on a single x86 core. Would the ALU be able to interleave say ADD and MULs? or would I incur the latency measure for each operation switch? I know that some ALU's have multiple ADD complexes, and I assume that would influence the answer, hence why I specified x86.
You need to be far more specific than x86, x86 is just the instruction set, the actual architecture can vary massively with the same instruction set.
In general though there is no penalty for interleaved operations.
Re: Execution units are often pipelined
#7What I am interested to know is who invented pipelining? I tried googling but without much success. Does anybody know?
Re: Execution units are often pipelined
#8What I am interested to know is who invented pipelining? I tried googling but without much success. Does anybody know?
Probably the first person to ask, 'how can I speed up this processor, maybe there's a way to do more than one processing step at a time for each instruction'
Re: Execution units are often pipelined
#9Is this still the case if I have different ALU operations. Say I have a single ALU on a single x86 core. Would the ALU be able to interleave say ADD and MULs? or would I incur the latency measure for each operation switch? I know that some ALU's have multiple ADD complexes, and I assume that would influence the answer, hence why I specified x86.
A modern ALU has multiple pipelined data paths for its operations. So maybe three adders with a one-cycle latency, two multipliers with a three-cycle latency, and one divider with a 16-cycle latency. Sustained throughput depends on the operation. Maybe one per cycle for add and multiply, but only one every eight cycle for divide.
Re: Execution units are often pipelined
#10What I am interested to know is who invented pipelining? I tried googling but without much success. Does anybody know?
Probably the first person to ask, 'how can I speed up this processor, maybe there's a way to do more than one processing step at a time for each instruction'
Presumably by analogy to production lines in factories?